Patents by Inventor Han-Chin Chiu
Han-Chin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9876093Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.Type: GrantFiled: June 7, 2016Date of Patent: January 23, 2018Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 9847401Abstract: A semiconductor device comprising a substrate, a channel layer over the substrate, an active layer over the channel layer and a laminate layer in contact with the active layer. The active layer has a band gap discontinuity with the channel layer.Type: GrantFiled: February 20, 2014Date of Patent: December 19, 2017Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
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Publication number: 20170271473Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.Type: ApplicationFiled: June 5, 2017Publication date: September 21, 2017Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Publication number: 20170271492Abstract: A semiconductor structure comprises a semiconductive substrate comprising a top surface, a III-V compound layer over the semiconductive substrate, and a first passivation layer over the III-V compound layer. The semiconductor structure also includes an etch stop layer over the first passivation layer. The semiconductor structure further includes a gate stack over the first passivation layer and surrounded by the etch stop layer.Type: ApplicationFiled: March 17, 2016Publication date: September 21, 2017Inventors: HAN-CHIN CHIU, SHENG-DE LIU, YU-SYUAN LIN, YAO-CHUNG CHANG, CHENG-YUAN TSAI
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Publication number: 20170263729Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The HEMT includes a first III-V compound layer having a first band gap and a second III-V compound layer having a second band gap over the first III-V compound layer, wherein the second band gap is greater than the first band gap. The HEMT further includes a first oxide layer over the second III-V compound layer; a first interfacial layer over the first oxide layer; and a passivation layer over the first interfacial layer.Type: ApplicationFiled: May 19, 2017Publication date: September 14, 2017Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
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Patent number: 9685525Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.Type: GrantFiled: August 11, 2016Date of Patent: June 20, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Patent number: 9666683Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The method includes epitaxially growing a first III-V compound layer and epitaxially growing a second III-V compound layer over the first III-V compound layer, wherein a first native oxide layer is formed on the second III-V compound layer. The method further includes in-situ treating the first native oxide layer with a first gas, thereby converting the first native oxide layer into a first crystalline oxide layer. The method further includes forming a first crystalline interfacial layer over the first crystalline oxide layer and forming a dielectric passivation layer over the first crystalline interfacial layer.Type: GrantFiled: October 9, 2015Date of Patent: May 30, 2017Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
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Patent number: 9633920Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.Type: GrantFiled: February 12, 2015Date of Patent: April 25, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Cheng-Yuan Tsai, Ming-Wei Tsai, Yao-Wen Chang, Wen-Yuan Hsieh
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Publication number: 20170104083Abstract: A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The method includes epitaxially growing a first III-V compound layer and epitaxially growing a second III-V compound layer over the first III-V compound layer, wherein a first native oxide layer is formed on the second III-V compound layer. The method further includes in-situ treating the first native oxide layer with a first gas, thereby converting the first native oxide layer into a first crystalline oxide layer. The method further includes forming a first crystalline interfacial layer over the first crystalline oxide layer and forming a dielectric passivation layer over the first crystalline interfacial layer.Type: ApplicationFiled: October 9, 2015Publication date: April 13, 2017Inventors: Han-Chin Chiu, Cheng-Yuan Tsai
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Publication number: 20170092738Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.Type: ApplicationFiled: December 13, 2016Publication date: March 30, 2017Inventors: Chen-Hao Chiang, Po-Chun Liu, Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu
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Patent number: 9601608Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.Type: GrantFiled: November 13, 2014Date of Patent: March 21, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ming-Wei Tsai, King-Yuen Wong, Han-Chin Chiu, Sheng-de Liu
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Patent number: 9564330Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.Type: GrantFiled: August 1, 2013Date of Patent: February 7, 2017Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
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Patent number: 9525054Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is smaller than the first band gap. The HEMT further includes a third III-V compound layer having a third band gap over the second III-V compound layer, wherein the third band gap is greater than the first band gap. A gate electrode is formed over the third III-V compound layer. A source region and a drain region are over the third III-V compound layer and on opposite sides of the gate electrode.Type: GrantFiled: January 4, 2013Date of Patent: December 20, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hao Chiang, Po-Chun Liu, Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu
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Publication number: 20160351684Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.Type: ApplicationFiled: August 11, 2016Publication date: December 1, 2016Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Publication number: 20160293723Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.Type: ApplicationFiled: June 7, 2016Publication date: October 6, 2016Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai
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Patent number: 9449867Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.Type: GrantFiled: June 17, 2014Date of Patent: September 20, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Tzu-Heng Wu, Yi-Hsien Chang, Kai-Chih Liang, Yi Heng Tsai, Wei-Cheng Shen, Chun-Ren Cheng, Chun-Wen Cheng, Han-Chin Chiu
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Patent number: 9425301Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.Type: GrantFiled: September 17, 2014Date of Patent: August 23, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Publication number: 20160240646Abstract: The present disclosure relates to a structure and method of forming a low damage passivation layer for III-V HEMT devices. In some embodiments, the structure has a bulk buffer layer disposed over a substrate and a device layer of III-V material disposed over the bulk buffer layer. A source region, a drain region and a gate region are disposed above the device layer. The gate region comprises a gate electrode overlying a gate separation layer. A bulk passivation layer is arranged over the device layer, and an interfacial layer of III-V material is disposed between the bulk passivation layer and the device layer in such a way that the source region, the drain region and the gate region extend through the bulk passivation layer and the interfacial layer, to abut the device layer.Type: ApplicationFiled: February 12, 2015Publication date: August 18, 2016Inventors: Han-Chin Chiu, Cheng-Yuan Tsai, Ming-Wei Tsai, Yao-Wen Chang, Wen-Yuan Hsieh
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Patent number: 9373689Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.Type: GrantFiled: December 28, 2012Date of Patent: June 21, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20160141404Abstract: A high-electron mobility transistor (HEMT) device employing a gate protection layer is provided. A substrate has a channel layer arranged over the substrate and has a barrier layer arranged over the channel layer. The channel and barrier layers define a heterojunction, and a gate structure is arranged over a gate region of the barrier layer. The gate structure includes a gate arranged over a cap, where the cap is disposed on the barrier layer. The gate protection layer is arranged along sidewalls of the cap and arranged below the gate between opposing surfaces of the gate and the cap. Advantageously, the gate protection layer passivates the gate, reduces leakage current along sidewalls of the cap, and improves device reliability and threshold voltage uniformity. A method for manufacturing the HEMT device is also provided.Type: ApplicationFiled: November 13, 2014Publication date: May 19, 2016Inventors: Ming-Wei Tsai, King-Yuen Wong, Han-Chin Chiu, Sheng-de Liu