Patents by Inventor Han-Chin Chiu
Han-Chin Chiu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9236464Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.Type: GrantFiled: November 20, 2014Date of Patent: January 12, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu, Po-Chun Liu, Han-Chin Chiu
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Patent number: 9224847Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.Type: GrantFiled: July 11, 2014Date of Patent: December 29, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
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Publication number: 20150364363Abstract: The present disclosure relates to an integrated microsystem with a protection barrier structure, and an associated method. In some embodiments, the integrated microsystem comprises a first die having a plurality of CMOS devices disposed thereon, a second die having a plurality of MEMS devices disposed thereon and a vapor hydrofluoric acid (vHF) etch barrier structure disposed between the first die and the second die. The second die is bonded to the first die at a bond interface region. The vHF etch barrier structure comprises a vHF barrier layer over an upper surface of the first die, and a stress reduction layer arranged between the vHF etch barrier layer and the upper surface of the first die.Type: ApplicationFiled: June 17, 2014Publication date: December 17, 2015Inventors: Tzu-Heng Wu, Yi-Hsien Chang, Kai-Chih Liang, Yi Heng Tsai, Wei-Cheng Shen, Chun-Ren Cheng, Chun-Wen Cheng, Han-Chin Chiu
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Patent number: 9214539Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.Type: GrantFiled: September 3, 2013Date of Patent: December 15, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, King-Yuen Wong, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20150318387Abstract: Some embodiments of the present disclosure relate to a high electron mobility transistor (HEMT) which includes a heterojunction structure arranged over a semiconductor substrate. The heterojunction structure includes a binary III/V semiconductor layer made of a first III-nitride material to act as a channel region of the e-HEMT, and a ternary III/V semiconductor layer arranged over the binary III/V semiconductor layer and made of a second III-nitride material to act as a barrier layer. Source and drain regions are arranged over the ternary III/V semiconductor layer and are spaced apart laterally from one another. A gate structure is arranged over the heterojunction structure and is arranged between the source and drain regions. The gate structure is made of a third III-nitride material. A first passivation layer is disposed about sidewalls of the gate structure and is made of a fourth III-nitride material.Type: ApplicationFiled: September 17, 2014Publication date: November 5, 2015Inventors: Han-Chin Chiu, Chi-Ming Chen, Cheng-Yuan Tsai, Fu-Wei Yao
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Patent number: 9130026Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).Type: GrantFiled: September 3, 2013Date of Patent: September 8, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20150236121Abstract: A semiconductor device comprising a substrate, a channel layer over the substrate, an active layer over the channel layer and a laminate layer in contact with the active layer. The active layer has a band gap discontinuity with the channel layer.Type: ApplicationFiled: February 20, 2014Publication date: August 20, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin CHIU, Hsing-Lien LIN, Cheng-Yuan TSAI
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Publication number: 20150123170Abstract: The present disclosure relates to a high electron mobility transistor compatible power lateral field-effect rectifier (L-FER) device. In some embodiments, the rectifier device has an electron supply layer located over a layer of semiconductor material at a position between an anode terminal and a cathode terminal. A layer of doped III-N semiconductor material is disposed over the electron supply layer. A passivation layer is located over the electron supply layer and the layer of doped III-N semiconductor material. A gate structure is disposed over the layer of doped III-N semiconductor material and the passivation layer. The layer of doped III-N semiconductor material modulates the threshold voltage of the rectifier device, while the passivation layer improves reliability of the L-FER device by mitigating current degradation due to high-temperature reverse bias (HTRB) stress.Type: ApplicationFiled: December 26, 2014Publication date: May 7, 2015Inventors: King-Yuen Wong, Ming-Wei Tsai, Han-Chin Chiu
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Publication number: 20150087118Abstract: A method of forming a high electron mobility transistor may include: forming a second III-V compound layer on a first III-V compound layer, the second III-V compound layer and the first III-V compound layer differing in composition; forming a p-type doped region in the first III-V compound layer; forming an n-type doped region in the second III-V compound layer, the n-type doped region overlying the p-type doped region; forming a source feature over the second III-V compound layer, the source feature overlying the n-type doped region; and forming a gate electrode over the second III-V compound layer, the gate electrode disposed laterally adjacent to the source feature.Type: ApplicationFiled: November 20, 2014Publication date: March 26, 2015Inventors: Chen-Hao Chiang, Chi-Ming Chen, Chung-Yi Yu, Po-Chun Liu, Han-Chin Chiu
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Publication number: 20150060873Abstract: Some embodiments of the present disclosure relates to a crystalline passivation layer for effectively passivating III-N surfaces. Surface passivation of HEMTs reduces or eliminates the surface effects that can otherwise degrade device performance. The crystalline passivation layer reduces the degrading effects of surface traps and provides a good interface between a III-nitride surface and an insulator (e.g., gate dielectric formed over the passivation layer).Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Chin Chiu, Trinh Hai Dang, Hsing-Lien Lin, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20150060861Abstract: Some embodiments of the present disclosure relates to a hybrid gate dielectric layer that has good interface and bulk dielectric properties. Surface traps can degrade device performance and cause large threshold voltage shifts in III-N HEMTs. This disclosure uses a hybrid ALD (atomic layer deposited)-oxide layer which is a combination of H2O-based and O3/O2-based oxide layers that provide both good interface and good bulk dielectric properties to the III-N device. The H2O-based oxide layer provides good interface with the III-N surface, whereas the O3/O2-based oxide layer provides good bulk properties.Type: ApplicationFiled: September 3, 2013Publication date: March 5, 2015Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Han-Chin Chiu, King-Yuen Wong, Cheng-Yuan Tsai, Chia-Shiung Tsai, Xiaomeng Chen
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Publication number: 20150034957Abstract: The present disclosure relates to an enhancement mode MISFET device. In some embodiments, the MISFET device has an electron supply layer located on top of a layer of semiconductor material. A multi-dielectric layer, having two or more stacked dielectric materials sharing an interface having negative fixed charges, is disposed above the electron supply layer. A metal gate structure is disposed above the multi-dielectric layer, such that the metal gate structure is separated from the electron supply layer by the multi-dielectric layer. The multi-dielectric layer provides fixed charges at interfaces between the separate dielectric materials, which cause the transistor device to achieve a normally off disposition.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Han-Chin Chiu, Hsing-Lien Lin, Cheng-Yuan Tsai
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Patent number: 8912570Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.Type: GrantFiled: August 9, 2012Date of Patent: December 16, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chen-Hao Chiang, Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu
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Patent number: 8884268Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.Type: GrantFiled: July 16, 2012Date of Patent: November 11, 2014Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chi-Ming Chen, Han-Chin Chiu, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20140319583Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.Type: ApplicationFiled: July 11, 2014Publication date: October 30, 2014Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
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Publication number: 20140231816Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.Type: ApplicationFiled: February 18, 2013Publication date: August 21, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
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Patent number: 8803158Abstract: A High Electron Mobility Transistor (HEMT) includes a first III-V compound layer having a first band gap, and a second III-V compound layer having a second band gap over the first III-V compound layer. The second band gap is greater than the first band gap. A crystalline interfacial layer is overlying and in contact with the second III-V compound layer. A gate dielectric is over the crystalline interfacial layer. A gate electrode is over the gate dielectric. A source region and a drain region are over the second III-V compound layer, and are on opposite sides of the gate electrode.Type: GrantFiled: February 18, 2013Date of Patent: August 12, 2014Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu, King-Yuen Wong
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Publication number: 20140209919Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.Type: ApplicationFiled: January 30, 2013Publication date: July 31, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin CHIU, Chen-Hao CHIANG, Chi-Ming CHEN, Chung-Yi YU
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Publication number: 20140183598Abstract: A semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A dielectric passivation layer is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on the second III-V compound layer, and extend through the dielectric passivation layer. A gate electrode is disposed over the second III-V compound layer between the source feature and the drain feature. The gate electrode has an exterior surface. An oxygen containing region is embedded at least in the second III-V compound layer under the gate electrode. A gate dielectric layer has a first portion and a second portion. The first portion is under the gate electrode and on the oxygen containing region. The second portion is on a portion of the exterior surface of the gate electrode.Type: ApplicationFiled: December 28, 2012Publication date: July 3, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Han-Chin Chiu, Chi-Ming Chen, Chung-Yi Yu, Chia-Shiung Tsai
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Publication number: 20140042446Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.Type: ApplicationFiled: August 9, 2012Publication date: February 13, 2014Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chen-Hao Chiang, Han-Chin Chiu, Po-Chun Liu, Chi-Ming Chen, Chung-Yi Yu