Abstract: A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Abstract: A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto.

Abstract: A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring.

Abstract: A method is provided for optimizing routing on a substrate such as an integrated circuit or printed circuit board. The method defines a plurality of parallel strips on an initial routing layout of conductors for a layer of an integrated circuit. Each conductor within each strip defines a brick. For each of the plurality of strips, a spacing between bricks and a brick thickness of each brick is adjusted as a function of i) a location of a brick in adjacent strips corresponding to the same conductor; ii) a desired brick thickness; and iii) a desired brick spacing.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes defining intracell wiring in at least one layer positioned above a substrate, the intracell wiring connecting to structures below the at least one layer and forming one or more terminals, and defining one or more candidate wires for at least one terminal to use as pre-defined intercell wiring for connection to the at least one terminal. The method further includes arranging selected cells from the cell library to form a desired layout of an integrated circuit, and routing intercell wiring so as to interconnect the selected cells to achieve a desired function of the integrated circuit including using only selected candidate wires for intercell wiring within borders of each of the selected cells.

Abstract: A method for simplifying metal shapes in an integrated circuit including receiving an incoming wire layout for at least one metal layer of an integrated circuit, the incoming wire layout for the at least one layer including a plurality of wires running in a preferred direction and a plurality of vias connected thereto.

Abstract: A method for configuring an integrated circuit including configuring a plurality cells to form a cell library, wherein configuring each cell includes routing a intracell wiring in at least one layer positioned above a substrate, with the conductors being spaced apart from one another so as to have gaps there between, and configuring and positioning a plurality of fill structures in the gaps. The method further includes arranging selected logic cells from the cell library to form a desired layout of the integrated circuit, routing interconnect wiring between the selected logic cells in the at least one layer, and removing fill structures at positions that conflict with the routing of the interconnect wiring.

Abstract: A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are ascertained and compared. Depending on the comparison result, the unaltered design data are retained or are replaced with altered design data. This method is carried out for a plurality of cycles in succession in order to optimize the design.

Abstract: A method is provided for optimizing routing on a substrate such as an integrated circuit or printed circuit board. The method defines a plurality of parallel strips on an initial routing layout of conductors for a layer of an integrated circuit. Each conductor within each strip defines a brick. For each of the plurality of strips, a spacing between bricks and a brick thickness of each brick is adjusted as a function of i) a location of a brick in adjacent strips corresponding to the same conductor; ii) a desired brick thickness; and iii) a desired brick spacing.

Abstract: In a method for forgery recognition in the fingerprint recognition, at first an image sequence is captured, which comprises a plurality of images of the fingerprint to be recognized. From at least two images capturing a texture captures a differential image. The texture will be compared with a predetermined texture in order to determine whether the captured image sequence comes from a real finger or from an imitation.

Abstract: A method is described in which design data are prescribed which stipulate a geometrical design for a component. The design is used to produce an altered geometrical design, for example through relocations in a region. For the two designs, assessment criteria are ascertained and compared. Depending on the comparison result, the unaltered design data are retained or are replaced with altered design data. This method is carried out for a plurality of cycles in succession in order to optimize the design.

Abstract: In a method for forgery recognition in the fingerprint recognition, at first an image sequence is captured, which comprises a plurality of images of the fingerprint to be recognized. From at least two images capturing a texture captures a differential image. The texture will be compared with a predetermined texture in order to determine whether the captured image sequence comes from a real finger or from an imitation.

Abstract: A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element.

Abstract: A capacitor in a semiconductor configuration, especially a DRAM, includes an electrode structure having a plurality of spaced-apart elements being electrically connected with a connecting structure and all including p-conductive material with a doping >10.sup.10 cm.sup.-3. The elements of the electrode structure are either stacked or disposed side by side and may be cup-shaped. In a production process, a layer sequence of alternatingly one p.sup.- -doped and one p.sup.+ -doped layer is produced, which receives an opening through the use of anisotropic etching. At least in a peripheral region of the opening, a p.sup.+ -zone is created, which connects the layer sequence and forms the connecting structure. Next, the p.sup.- -doped layers are etched selectively to the p.sup.+ -doped layers, a capacitor dielectric is deposited, and a counterelectrode is produced.

Abstract: An apparatus for the chemical-mechanical polishing of wafers has a rotating disk provided with a polishing body, a supply device for a polishing fluid and a holding device for the wafer. An axis of the disk runs parallel to the surface of the wafer. A cylindrical edge surface of the disk is provided with the polishing body in such a way that a trench with a specific cross section can be made in the wafer.

Abstract: A semiconductor array with self-adjusted contacts includes a substrate having a surface, at least two mutually spaced-apart doped regions extending in a first lateral direction on the surface, and insulated regions each being associated with a respective one of the doped regions and extending in the first lateral direction on the same side. Contact surfaces each extend in the first lateral direction above a respective one of the doped regions and at least partially above the insulated region associated with the one doped region. An insulating layer has contact holes each being formed therein above a respective one of the contact surfaces for receiving a self-adjusted contact. A method for producing a semiconductor array with self-adjusted contacts includes producing one of the contact surfaces with a first fragment being a part of the contact surface extending above the doped region and a second fragment being a part of the contact surface extending above the insulated region.

Abstract: A memory device includes a multiplicity of memory cells disposed on a substrate for at least intermittent stable storage of at least two different information states. A writing device is associated with the memory cells for selectively putting one of the multiplicity of memory cells into a predetermined information state by external action. A reading device is associated with the memory cells for external detection of a current or chronologically preceding information state of a selected memory cell. The memory cells have a miniaturized mechanical element.

Abstract: A method for producing a contact hole to a first doped region of a first conductivity type in a semiconductor wafer having doped regions of the first and of a second conductivity type, includes producing a first doped region in a substrate having a surface, and bounding the first doped region with insulation regions at least at the surface of the substrate. A diffusion barrier layer is produced leaving at least the first doped region free and covering a second doped region of a second conductivity type. An undoped silicon layer is deposited over the entire surface. A doped region is selectively produced in the silicon layer by implantation, and the doped region overlaps a region for a contact hole. Undoped portions of the silicon layer are selectively removed relative to the doped region. An insulation layer is produced over the entire surface. A contact hole is opened in the insulation layer by selective anisotropic etching relative to the doped region of the silicon layer.