Abstract: A semiconductor memory configuration and a manufacturing process for the semiconductor memory configuration use a polishing process in the manufacture of a semiconductor memory configuration with stacked-capacitor-above-bit-line memory cells. At least TC pillars are created with the aid of a CMP step and a completely planarized surface existing prior to the manufacture of the bit line. Further CMP steps are advantageously used, inter alia, in the manufacture of a TB pillar of a bit line which is countersunk in a trench and of a lower capacitor plate, as well as to completely planarize a cell array and a periphery prior to interconnection of the circuit.

Abstract: For the global planarization of a semiconductor circuit or a micromechanical component with a step between a higher-lying region and a lower-lying region, the regions being large in area, it is envisaged to deposit a first layer (50), remove it again in the higher-lying region apart from a rib (50), deposit a second layer (51) and then, in a CMP step, planarize the entire arrangement.

Abstract: An improved method for manufacturing a bit line via hole for a memory cell is disclosed wherein changes in the topography of a conductive layer forming the cell plate that are caused by the capacitor are utilized for producing an etching mask for the bit line via hole. A depression is formed because the second source/drain region of the transistor which is to be contacted by the bit line is not covered by the lower capacitor plate. The etching mask is not produced in the depression but only at the raised locations and is therefore self-aligned above the second S/D region.

Abstract: A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4") are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.

Abstract: A self-aligned through hole (5), particularly a bit line through hole to a source/drain region (2) that is self-aligned relative to the word line, is produced in neighboring word lines (3a) having a greater spacing from one another in the proximity of the source/drain region than at other locations. Narrow spacings are completely filled by surface-wide deposition of an insulating intermediate layer and subsequent, anisotropic etching, whereas insulating spacers (4") are formed in enlarged interspaces at side walls of the encapsulated word lines (3) and thereby form a self-aligned through hole.

Abstract: The arrangement has storage cells consisting of MOS transistors and trench capacitors, the trench (7) being produced in a self-adjusted manner with respect to primary word lines (4) and insulation regions (2). Both capacitor electrodes are arranged within the trench, the first electrode being connected via a contact on the trench wall to the selection transistor. A bit line (20,21), which runs partially above and partially in the trench and is insulated from the second electrode (16) by a third and a fourth insulating layer (17,18) has a contact at this point to the conductive region of the adjacent selection transistor. The storage matrix is composed of rows of storage cells running in the direction of the bit line, the storage cells located in the same row having the selection transistor on a defined side of the capacitor, and on the opposite side in the adjacent row.

Abstract: The arrangement relates to bit lines which are widened to form contact surfaces (11, 21, 31, 41, 51) at the contacts (10, 20, 30, 40, 50) to underlying cells, the contacts being arranged in an at least a three-fold stagger. A minimum space requirement is achieved in conjunction with increased reliability when the distance b.sub.Sp between edges of adjacent bit lines has the same value everywhere, and the contact surfaces can thereby be enlarged.

Abstract: A conductor track configuration for very large-scale integrated circuits includes at least two lower conductor tracks extending substantially in a first direction and at least two upper conductor tracks extending substantially in the first direction above the lower conductor tracks. Each of the lower conductor tracks is subdivided into segments, defining gaps between the segments. Each respective one of the segments has one contact leading to the upper conductor track disposed above the one segment. The lower conductor tracks adjacent the segments, as seen in a second direction, have one of the gaps at least in the vicinity of one of the contacts.