Abstract: A source-camera assembly with an isolated light path for a reference pixel is described. The assembly may include a projector, a camera assembly, a reference waveguide, and an overmold. The projector may include a source array configured to emit light and a lens assembly configured to direct the light into a local area. The camera assembly may include a sensor and a reference pixel. The sensor may be configured to detect the emitted light reflected from an object within the local area. The reference waveguide is configured to guide a portion of the light emitted by the projector from the source array to the reference pixel. The light detected by the sensor and the light detected by the reference pixel may be used to determine depth information for the object. The overmold is opaque to the emitted light and covers portions of the projector, the camera assembly, and the reference waveguide.

Abstract: An electronic device includes an optical transmitter, an optical receiver, a memory, an optical transmitter controller, and an optical receiver controller. The memory is configured to store an indicator of a next pulse repetition interval (PRI) and a set of parameters associated with operating the optical transmitter in accordance with the next PRI. The optical transmitter controller is configured to retrieve the indicator of the next PRI in response to a trigger signal; retrieve, using the indicator of the next PRI, the set of parameters; and operate the optical transmitter in accordance with the set of parameters. The optical receiver controller is configured to operate the optical receiver; update the indicator of the next PRI stored in the memory; and provide the trigger signal to the optical transmitter controller.

Abstract: An optoelectronic system includes a transmit side and a receive side. The transmit side and the receive side each include an oversampled phase locked loop configured to receive a decimated system clock signal. Each phase-locked loop is configured to output a high frequency sampling clock signal that, in the case of the transmit side, may be leveraged to generate an arbitrary current waveform that, in turn, can be delayed by a delay-locked loop before being applied to a current-controlled light emitting element. The receive side can generate a clock signal at the same high frequency as the transmit side and can be configured to trigger a reset of the transmit side so that the high frequency clock signals between the transmit and receive sides are synchronized.

Abstract: Apparatus for optical sensing includes an illumination assembly, which directs first optical radiation toward a target scene over a first range of angles and second optical radiation over at least one second range of angles, which is smaller than and contained within the first range, while modulating the optical radiation with a carrier wave having at least one predetermined carrier frequency. A detection assembly includes an array of sensing elements, which output respective signals in response to the first and the second optical radiation. Processing circuitry drives the illumination assembly to direct the first and the second optical radiation toward the target scene in alternation, and processes the signals output by the sensing elements in response to the first optical radiation in order to compute depth coordinates of points in the target scene, while correcting the computed depth coordinates in response to the second optical radiation.

Abstract: An arbitrary current waveform generator operates by oversampling an input clock signal, and decimating the oversampled clock signal to a decimated clock signal. The oversampled clock signal can be provided as a clock signal to a shift register preloaded with digital values corresponding to samples of a selected waveform to provide as output, and the decimated clock signal can be used to maintain phase synchronization with the input clock signal. Digital output of the shift register is provided to a digital to analog converter, output from which may be used to drive a current-controlled electronic circuit element.

Abstract: Sensing apparatus includes a radiation source, which emits pulses of optical radiation toward multiple points in a target scene. A receiver receives the optical radiation that is reflected from the target scene and outputs signals that are indicative of respective times of flight of the pulses to and from the points in the target scene. Processing and control circuitry selects a first pulse repetition interval (PRI), a second PRI, greater than the first PRI, and a third PRI, greater than the second PRI, from a permitted range of PRIs, drives the radiation source to emit sequences of the pulses at the first PRI, the second PRI, and the third PRI, and processes the signals output by the receiver in response to the first, second, and third sequences of the pulses in order to compute respective depth coordinates of the points in the target scene.

Abstract: A configurable AC/DC readout architecture that can be operated in an AC measurement mode or a DC measurement mode is disclosed. The configurable AC/DC architecture can utilize shared circuitry such as amplifiers and analog-to-digital converters (ADCs). The configurable AC/DC readout can be used other sensor configurations where both AC and DC measurement signals can captured and require readout and conversion to digital signals. The configurable AC/DC readout architecture can include a filter configured to filter out a DC signal component in the AC measurement mode. The configurable AC/DC readout architecture can include a bypass witch to bypass the filter in the DC measurement mode. A programmable gain amplifier can adjust the signal amplitude of DC or AC signals to allow use of a shared analog-to-digital converter.

Abstract: An optoelectronic device includes a laser diode, a driver and a reverse-bias circuit. The laser diode has a first terminal and a second terminal. The driver is coupled to drive current pulses through the laser diode between the first and second terminals. The reverse-bias circuit is configured to reverse-bias the laser diode during time intervals derived from the current pulses.

Abstract: An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Abstract: A configurable AC/DC readout architecture that can be operated in an AC measurement mode or a DC measurement mode is disclosed. The configurable AC/DC architecture can utilize shared circuitry such as amplifiers and analog-to-digital converters (ADCs). The configurable AC/DC readout can be used other sensor configurations where both AC and DC measurement signals can captured and require readout and conversion to digital signals. The configurable AC/DC readout architecture can include a filter configured to filter out a DC signal component in the AC measurement mode. The configurable AC/DC readout architecture can include a bypass witch to bypass the filter in the DC measurement mode. A programmable gain amplifier can adjust the signal amplitude of DC or AC signals to allow use of a shared analog-to-digital converter.

Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

Abstract: A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Abstract: An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Abstract: Embodiments herein describe a 3D flash memory system that includes multiple blocks where each block contains multiple pages arranged in a vertical stack. Instead of having a single command line indicating whether a read or program is to be performed, separate command lines are coupled to each of the blocks. As a result, if the memory system identifies a read request and a program request to different blocks, the requests can be performed in parallel. In one embodiment, a program command line is used to perform a program request on a first block while a read command line is used to perform a read request on a second block in the 3D flash memory system in parallel. Furthermore, because a program request can take much longer to complete than a read request, the 3D flash memory system can perform multiple read requests in parallel with the program request.

Abstract: An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

Abstract: Embodiments herein describe a memory system that queues program requests to a block of flash memory until a predefined threshold is reached. That is, instead of performing program requests to write data into the block as the requests are received, the memory system queues the requests until the threshold is satisfied. Once the buffer for the block includes the threshold amount of program requests, the memory system performs the stored requests. In one embodiment, the memory system erases all the pages in the block before writing the new data in the program requests into the destination pages. The data that was originally stored in the pages that are not destination pages is rewritten into the pages. In this example, the queued program requests can be written into the pages using one erase and write step rather than individual erase and write steps for each of the requests.

Abstract: Embodiments herein describe a 3D flash memory system that includes multiple blocks where each block contains multiple pages arranged in a vertical stack. Instead of having a single command line indicating whether a read or program is to be performed, separate command lines are coupled to each of the blocks. As a result, if the memory system identifies a read request and a program request to different blocks, the requests can be performed in parallel. In one embodiment, a program command line is used to perform a program request on a first block while a read command line is used to perform a read request on a second block in the 3D flash memory system in parallel. Furthermore, because a program request can take much longer to complete than a read request, the 3D flash memory system can perform multiple read requests in parallel with the program request.