Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Abstract: A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, Rfb, and feedback capacitor, Cfb, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R2 and R2?, and wherein the other side of the feedback capacitor is coupled between R2? and the output of the first amplifier, R2 is connected to Vbias from one side and Rfb and R2? from the other, R2? is connected to Rfb and R2 from one side and Cfb and output of the first amplifier from the other side, another resistor, R1, is connect to the output of the first amplifier, Cfb and R2? from one side and R1?, yet another resistor, and input of amp2 from the other, a second amplifier, Amp2, is connected to the R1 and R1? at one input and 1.

Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Abstract: A display panel includes multiple pixel elements for composing an image and a control circuit for accessing each pixel element. The control circuit includes a data line for conducting a luminance signal and a selection line for conducting a selection signal. Each pixel element includes a switch, a display cell, and a compensatory capacitor. The switch is connected to the data line and the selection line, such that the switch can selectively deliver the luminance signal to the display cell. The display cell is configured to adjust its light transmittance in response to the received luminance signal. Being connected to the switch and the display cell, the compensatory capacitor is configured to receive a compensation signal corresponding to a transition of the selection signal and for correcting a parasitic effect at the display cell.

Abstract: An inductor conducts a first current, which is variable. A first transistor is coupled through the inductor to an output node. The first transistor alternately switches on and off in response to a voltage signal, so that the first current is: enhanced while the first transistor is switched on in response to the voltage signal; and limited while the first transistor is switched off in response to the voltage signal. A second transistor is coupled to the first transistor. The second transistor conducts a second current, which is variable. On/off switching of the second transistor is independent of the voltage signal. Control circuitry senses the second current and adjusts the voltage signal to alternately switch the first transistor on and off in response to: the sensing of the second current; and a voltage of the output node.

Abstract: A circuit with a single capacitor and multiple outputs. The circuit reuses the same flying capacitor to charge multiple rails by timing the charging cycle sequentially, where the one rail is charged and then the charge pump switches to deliver power to the second rail.

Abstract: A circuit for a level shifting of common mode voltage. The circuit includes a first amplifier, wherein the input of the first amplifier is coupled to a voltage source and another input of the first amplifier is coupled 2.5v, feedback resistor, Rfb, and feedback capacitor, Cfb, connected coupled to the voltage source, wherein other side of feedback resistor is coupled between two resistors, R2 and R2?, and wherein the other side of the feedback capacitor is coupled between R2? and the output of the first amplifier, R2 is connected to Vbias from one side and Rfb and R2? from the other, R2? is connected to Rfb and R2 from one side and Cfb and output of the first amplifier from the other side, another resistor, R1, is connect to the output of the first amplifier, Cfb and R2? from one side and R1?, yet another resistor, and input of amp2 from the other, a second amplifier, Amp2, is connected to the R1 and R1? at one input and 1.

Abstract: A switch-mode DC-DC voltage converter including a boost stage in the form of a charge pump and a buck stage. Control circuitry is provided that enables the operation of the buck stage while the charge pump stage is also enabled, followed by disabling of the charge pump stage as the input voltage and output voltage increase. The buck converter stage is constructed so that it regulates the output voltage at a voltage above that which disables the charge pump stage. Conduction losses in the main current path, due to the necessity of a power FET or other switching device, are avoided.

Abstract: An integrated analog data receiver for a capacitive touch screen. An analog data receiver circuit for a touch screen device is provided including a sigma delta analog to digital converter configured for direct connection to an analog output of a touch screen device, and further including an integrator circuit having an input coupled for receiving the analog output signal and outputting an integrated output voltage; a comparator coupled to the integrated output voltage and a first bias voltage and outputting a comparison voltage; a clocked sampling latch coupled to the comparison voltage and to a clock signal and outputting quantized data bits corresponding to samples of the comparison voltage; and a digital filter and decimator coupled to the clocked sampling latch and outputting serial data bits which form a digital representation corresponding to the output of the touch screen device. Additional circuits and systems are disclosed.

Abstract: A bandpass sense amplifier circuit (FIG. 2A) is disclosed. The circuit includes a capacitor (C0) having a first terminal coupled to receive an input signal (Vin) and a second terminal. A current conveyor circuit (200-206,212) has a third terminal (X) coupled to the second terminal of the capacitor and a fourth terminal (Z) arranged to mirror a current into the third terminal. A voltage follower circuit (214) has an input terminal coupled to the fourth terminal of the current conveyor circuit and an output terminal.

Abstract: A circuit includes an input stage configured to receive a regulated input signal and generate an input stage output signal in response to the regulated input signal. An isolation stage can be configured to pass the input stage output signal to a buffered output node. The isolation stage receives feedback from the buffered output node to deactivate the buffer input stage if transient voltages are generated at the buffered output node. An output stage can be configured to provide current to the buffered output node in response to the regulated input signal.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22,TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Abstract: Circuitry (10-2) for limiting the maximum amount of current (IREF) flowing through a first electrode (DRAIN) of a first transistor (T1) includes an amplifier (14) having an output coupled by a conductor (19) to a control electrode of the first transistor and limiting circuitry (17) including reference current sensing circuitry (22, TSENSE) having a reference current source (IREF—SENSE). A reference current sensing transistor (TSENSE) has a control electrode coupled to the control electrode of the first transistor, a first electrode coupled to a terminal (20) of the reference current source, and a second electrode (SOURCE) coupled to a second electrode of the first transistor. A buffer (T2) has an input coupled to the terminal of the reference current source. The maximum amount is limited in accordance with the reference current source to prevent an increase in magnitude of voltage applied by the amplifier to the first transistor.

Abstract: A voltage regulator controls a regulated output voltage (Vout) by feeding it back to a differential input stage (13) receiving a reference voltage (Vref) and applying an output (3) to a control electrode of a follower transistor (M4) that is coupled to an output stage (15) which generates the output voltage (Vout). The output stage operates pull-up (M7B) and pull-down (M5B) transistors in response to a signal (6A) produced by the follower transistor (M4) during normal regulation operation, and provides fast settling of the output voltage by turning on a transient pull-up transistor (M7A) or transient pull-down transistor (M5A) in response to the signal (6A) produced by the follower transistor (M4) during a fast increasing or decreasing transition, respectively, of the load current (IL). A filtering resistor (RFLT) is coupled between the output voltage and a common electrode of the transient pull-up and pull down transistors.

Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.

Abstract: A comparator (10) includes a first input transistor (M0) having a drain coupled to a gate and drain of a first diode-connected transistor (M2) and a gate of a first current mirror output transistor (M4), and a second input transistor (M1) having a drain coupled to a gate and drain of a second diode-connected transistor (M3) and a gate of a second current mirror output transistor (M5). Sources of the first and second current mirror output transistors are connected to a supply voltage (VDD). Gates of the first and second input transistors are coupled to first (VIN?) and second (VIN+) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M8,M9) is coupled to the drains of the first and second current mirror output transistors.

Abstract: A voltage follower circuit including an input stage for generating a difference between the input signal and the output signal. An output circuit receiving the first signal and producing the output signal. A slew boost circuit includes a first transistor having a control electrode for receiving the input signal, a first electrode coupled to a first current source, and a second electrode coupled to a first supply voltage, a second transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to the first supply voltage, and a third transistor having a control electrode coupled to the first electrode of the first transistor, a first electrode coupled to the first signal, and a second electrode coupled to a second supply voltage.