Abstract: A voltage regulator controls a regulated output voltage (Vout) by feeding it back to a differential input stage (13) receiving a reference voltage (Vref) and applying an output (3) to a control electrode of a follower transistor (M4) that is coupled to an output stage (15) which generates the output voltage (Vout). The output stage operates pull-up (M7B) and pull-down (M5B) transistors in response to a signal (6A) produced by the follower transistor (M4) during normal regulation operation, and provides fast settling of the output voltage by turning on a transient pull-up transistor (M7A) or transient pull-down transistor (M5A) in response to the signal (6A) produced by the follower transistor (M4) during a fast increasing or decreasing transition, respectively, of the load current (IL). A filtering resistor (RFLT) is coupled between the output voltage and a common electrode of the transient pull-up and pull down transistors.

Abstract: A method is provided. A first reference voltage during an idle mode is selected, and the first reference voltage is applied to a switched-mode converter. A first output voltage is then generated by the switched-mode converter from a power supply, and a capacitor is overcharged with the first output voltage. The first output voltage is regulated to generate a second output voltage during the idle mode. Then, a second reference voltage during a quiet mode, where the second reference voltage to the buck converter. During the quiet mode, a third output voltage is generated from the switched-mode converter and from discharging the overcharged capacitor, and the third output voltage is regulated to generate the second output voltage.

Abstract: A method is provided. A low dropout regulator (LDO) is disabled during a first mode, and a first reference voltage is selected and applied to a switched-mode converter during the first mode. Also during the first mode, a first output voltage is generated by the switched-mode converter from a power supply, and a first capacitor is overcharged with the first output voltage. The LDO is then enabled during a second mode. During a first portion of a startup period for the second mode, a second capacitor is charged from the first capacitor, and a second reference voltage is selected and applied to the switched-mode converter. Then, during a second portion of the startup period for the second mode, the second capacitor is charged with the switched-mode converter.

Abstract: A comparator (10) includes a first input transistor (M0) having a drain coupled to a gate and drain of a first diode-connected transistor (M2) and a gate of a first current mirror output transistor (M4), and a second input transistor (M1) having a drain coupled to a gate and drain of a second diode-connected transistor (M3) and a gate of a second current mirror output transistor (M5). Sources of the first and second current mirror output transistors are connected to a supply voltage (VDD). Gates of the first and second input transistors are coupled to first (VIN?) and second (VIN+) input signals, respectively. Sources of the first and second diode-connected transistors are coupled to drains of the first and second current mirror output transistors, respectively. A latch circuit (M8,M9) is coupled to the drains of the first and second current mirror output transistors.

Abstract: A programmable gain low noise amplifier includes a tail current transistor (Q3) having a source coupled to a first reference voltage (VDD) and a drain coupled to a tail current conductor (18) and, in a differential input embodiment, a plurality of pairs (Q4,5, Q7,8, Q10,11, Q13,14) of differentially coupled input transistors. Each pair includes a first input transistor having a gate coupled to a first input conductor (19A) and a drain coupled to a first output conductor (26A) and a second input transistor having a gate coupled to a second input conductor (19B), a source coupled to a source of the first transistor, and a drain coupled to a second output conductor (26B). The sources of the first and second input transistors of some or all of the pairs are selectively coupled to the tail current conductor (18) in it response to corresponding gain control signals (B1,2,3).

Abstract: A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Abstract: A method and circuit for facilitating control of the AC coupling for addressing input offset in an amplifier circuit are provided. In accordance with an exemplary embodiment, a control circuit comprises a pair of resistive networks coupled together through a capacitive coupling, with the pair of resistive networks configured between two amplifier devices of the amplifier circuit. The capacitive coupling is configured to prevent offset in the differences between input voltages to the two amplifier devices, and can comprise various types and configurations of capacitor networks, devices and components. The pair of resistive networks is configured to generate an output current signal from the two amplifier devices while facilitating a substantially identical capacitive loading on the two amplifier devices.

Abstract: A programmable gain low noise amplifier includes a tail current transistor (Q3) having a source coupled to a first reference voltage (VDD) and a drain coupled to a tail current conductor (18) and, in a differential input embodiment, a plurality of pairs (Q4,5, Q7,8, Q10,11, Q13,14) of differentially coupled input transistors. Each pair includes a first input transistor having a gate coupled to a first input conductor (19A) and a drain coupled to a first output conductor (26A) and a second input transistor having a gate coupled to a second input conductor (19B), a source coupled to a source of the first transistor, and a drain coupled to a second output conductor (26B). The sources of the first and second input transistors of some or all of the pairs are selectively coupled to the tail current conductor (18) in it response to corresponding gain control signals (B1,2,3).

Abstract: An amplifier with a electrically controllable gain and enhanced protection against an overload condition is disclosed. The amplifier contains a buffer amplifier configured to convert an input voltage signal to a current signal and an output amplifier that converts a current signal to an output voltage signal. The gain of the amplifier can be controlled by an internal resistor that can be electrically configured to different resistance levels. The amplifier also includes a clamping network used to clamp the output amplifier to prevent an overload condition. This network may take the form of a diode network. Such an amplifier may take the form of a differential amplifier.

Abstract: An amplifier with a electrically controllable gain and enhanced protection against an overload condition is disclosed. The amplifier contains a buffer amplifier configured to convert an input voltage signal to a current signal and an output amplifier that converts a current signal to an output voltage signal. The gain of the amplifier can be controlled by an internal resistor that can be electrically configured to different resistance levels. The amplifier also includes a clamping network used to clamp the output amplifier to prevent an overload condition. This network may take the form of a diode network. Such an amplifier may take the form of a differential amplifier.