Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.

Abstract: A memory system according to the embodiment comprises a cell array of plural cells having three or more settable physical quantity levels and operative to store a code composed of symbols expressed by elements in a finite field Zp (p is a prime), wherein a set of two cells is defined as a pair cell and a combination of physical quantity levels of the two cells contained in the pair cell is defined as a pair cell level, wherein the pair cell uses a pair cell level of plural pair cell levels, which maximizes or minimizes a physical quantity level of one cell contained in the pair cell, to assign elements in the Zp to the pair cell levels, thereby storing symbols of the code.

Abstract: An absorbent article ensuring that even when excreted urine diffuses by running down the wearer's skin, the urine is prevented from leaking out of the absorbent article. The absorbent article comprises an absorbent sheet that has at least one absorbent polymer-existing region in which the absorbent polymer is sandwiched by at least one liquid-pervious sheet and at least one absorbent polymer-nonexisting region which is free of absorbent polymer. The at least a part of the absorbent sheet is disposed in a rear waist region, and a planar shape of the absorbent polymer-existing region disposed on the rear waist region side of the longitudinal center of the crotch region of the absorbent sheet is a nearly V-shaped with an apex facing in the direction from the front waist region to the rear waist region in the longitudinal direction of the absorbent article.

Abstract: A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.

Abstract: A disposable wearing article has a skin-contactable sheet moveable relative to a chassis. The chassis includes an inner sheet, an outer sheet and a liquid-absorbent panel interposed between these inner and outer sheets. The absorbent panel lies at least in the crotch region and extends into the front and rear waist regions in the longitudinal direction. In the rear waist region, a skin-contactable sheet adapted to come in contact with the wearer's skin is attached to the inner surface of the inner sheet. The skin-contactable sheet has front and rear ends extending in the transverse direction and lateral portions extending in the longitudinal direction and only the lateral portions are bonded to the inner sheet.

Abstract: A memory system according to the embodiment comprises a cell array including plural unit cell arrays stacked, each unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines; and an access circuit operative to write data in the memory cell, wherein the access circuit partly has a first part formed at the same height as that of a certain unit cell array in the stacking direction of the plural unit cell arrays and on the periphery of the certain unit cell array.

Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different physical states; and an access circuit operative to make access to the memory cell via the first line and the second line, wherein the access circuit, on writing data in the access cell, uses a non-access-side first line driver to electrically connect a non-access first line adjacent to an access first line to a first potential power supply via a diode-connected transistor.

Abstract: A memory system according to the embodiment comprises a cell array including a unit cell array, the unit cell array containing plural first lines, plural second lines intersecting the plural first lines, and plural memory cells provided at the intersections of the plural first lines and the plural second lines and operative to store data in accordance with different resistance states; and an access circuit operative to execute a write sequence of changing the resistance state for writing data in the memory cell, wherein the access circuit, on the write sequence, executes a first step of changing all memory cells provided at the intersections of access first lines and the access and fault second lines to the high resistance state, and a second step of changing all or part of access cells connected to the access second line to the low resistance state.

Abstract: A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.

Abstract: A resistance change memory device includes: a memory cell formed of a variable resistance element and a diode connected in series, the state of the variable resistance element being reversibly changed in accordance with applied voltage or current; and a stabilizing circuit so coupled in series to the current path of the memory cell as to serve for stabilizing the state change of the memory cell passively.

Abstract: A memory system according to the embodiment comprises a cell array of unit cell arrays each including memory cells; and an access circuit, wherein the memory cell changes from a first resistance state to a second resistance state on application of a first polarity voltage, and changes from the second resistance state to the first resistance state on application of a second polarity voltage, the access circuit provides the first and second lines connected to an access-targeted memory cell with access potentials, and brings at least one of the first and second lines connected to an access-untargeted memory cell into a floating state to make access to the access-targeted memory cell, the unit cell array includes first spare lines to provide redundancy for the first lines, and an alignment of the first lines includes a certain number of the first spare lines arranged in a certain cycle.

Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.

Abstract: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell array including blocks, each block being capable of executing a write, read, or erase operation independently of other blocks. A control portion is configured to execute the operation of a first block among the blocks in a first cycle, set a selection inhibited region within a range of a predetermined distance from the first block, until a temperature relaxation time for relaxing a temperature of the first block has elapsed, set a region except the selection inhibited region among the blocks as a second block, and execute the operation of the second block in a second cycle.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: A semiconductor memory device comprises a memory cell array including plural memory cells provided at the intersections of plural first lines and plural second lines; and a write circuit. The write circuit, on execution of a write operation, executes a first step of applying a voltage across the first and second lines connected to a data-write-targeted, selected memory cell, and a different voltage across the first and second lines connected to a data-write-untargeted, unselected memory cell of the plural memory cells and, after execution of the first step, executes a second step of applying a voltage, required for data write, across the first and second lines connected to the selected memory cell, and bringing at least one of the first and second lines connected to the unselected memory cell into the floating state.

Abstract: According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: The present invention aims to provide a wearing article improved so that various types of nonwoven fabrics can be effectively used for target nonwoven fabric without anxiety that the target nonwoven fabric once engaged with hook elements might be readily torn. As an outer sheet 8 defining a garment-facing side of a chassis 2, a commonly-used nonwoven fabric is used and this nonwoven fabric is oriented in a longitudinal direction Y. Rear waist region's side edges 14 of the chassis 2 are provided with flaps 16 attached thereto. Each of the flaps 16 has a joint region 19 along which the flap 16 is joined to the chassis 2 and first and second hook elements 21, 22. Between the joint region 19 and the first and second hook elements 21, 22 as viewed in the transverse direction X, a contractible region 23 adapted to be contractible in the transverse direction X. The contractible region 23 is provided with a plurality of flap's elastic members 24.

Abstract: A memory system according to the embodiment comprises a cell array including cell units having p or more physical quantity levels (p is a prime of 3 or more); a code generator unit operative to convert binary-represented input data to a write code represented by elements in Zp that is a residue field modulo p; and a code write unit operative to write the write code in the cell unit in accordance with the association of the elements in Zp to different physical quantity levels, wherein the input data is recorded in (p?1) cell units, the (p?1) cell units including no cell unit that applies the same physical quantity level for write in the case where the input data is 0 and for write in the case where only 1 bit is 1.