Patents by Inventor Haruki Toda

Haruki Toda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Memory device with error correction system for detection and correction errors in read out data
    Patent number: 8291303
    Abstract: There is disclosed a memory device with an error detection and correction system formed therein, the error detection and correction system being configured to detect and correct errors in read out data by use of a BCH code, wherein the error detection and correction system is 4-bit error correctable, and searches error locations in such a way as to: divide an error location searching biquadratic equation into two or more factor equations; convert the factor equations to have unknown parts and syndrome parts separated from each other for solving them; and compare indexes of the solution candidates with those of the syndromes, the corresponding relationships being previously obtained as a table, thereby obtaining error locations.
    Type: Grant
    Filed: August 12, 2008
    Date of Patent: October 16, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Memory device having variable resistance memory cells disposed at crosspoint of wirings
    Patent number: 8269207
    Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.
    Type: Grant
    Filed: May 3, 2011
    Date of Patent: September 18, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • MEMORY SYSTEM AND MEMORY CONTROLLER
    Publication number: 20120233383
    Abstract: A memory system according to the embodiment comprises a memory device including a plurality of memory cells operative to store storage data, the storage containing input data from external to which parity information is added; and a memory controller operative to convert between the input data and the storage data, the storage data containing information data corresponding to the input data, and a relationship between the information data and the input data being nonlinearly.
    Type: Application
    Filed: February 7, 2012
    Publication date: September 13, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • Semiconductor integrated circuit device having memory cells disposed at cross point of metal lines and method for fabricating the same
    Patent number: 8258496
    Abstract: A semiconductor integrated circuit device including: a semiconductor substrate on which a circuit is formed; a plurality of functional device arrays stacked on the semiconductor substrate; and vertical wirings so disposed outside of the functional device arrays as to couple the signal lines of the functional device arrays to the circuit, wherein the vertical wirings include multi-layered metal pieces, each layer of which has a plurality of the metal pieces dispersedly arranged in a stripe-shaped contact trench formed on an interlayer insulating film in the elongated direction.
    Type: Grant
    Filed: March 16, 2009
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Akiko Nara
  • Nonvolatile semiconductor memory device generating different write pulses to vary resistances
    Patent number: 8259489
    Abstract: A nonvolatile semiconductor memory device comprises a memory cell array of electrically erasable programmable nonvolatile memory cells arranged in matrix, each memory cell using a variable resistor. A pulse generator is operative to generate plural types of write pulses for varying the resistance of the variable resistor in three or more stages based on ternary or higher write data. A selection circuit is operative to select a write target memory cell from the memory cell array based on a write address and supply the write pulse generated from the pulse generator to the selected memory cell.
    Type: Grant
    Filed: September 9, 2008
    Date of Patent: September 4, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Nagashima, Hirofumi Inoue, Haruki Toda
  • Resistance change memory device
    Patent number: 8243493
    Abstract: A resistance change memory device includes: a semiconductor substrate; a cell array so formed on the substrate as to have resistance-change memory cells three-dimensionally stacked and arranged; and a sense amplifier array formed on the substrate under the cell array, wherein the cell array includes first and second cell array blocks arranged in a bit line direction, and first and second bit lines are selected from the first and second cell array blocks, respectively, to constitute a pair and coupled to differential input nodes in the sense amplifier array.
    Type: Grant
    Filed: May 28, 2008
    Date of Patent: August 14, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Phase change memory device
    Patent number: 8237143
    Abstract: A memory device has a semiconductor substrate; a plurality of cell arrays stacked above the substrate, each cell array having memory cells, bit lines each commonly connecting one ends of plural cells arranged along a first direction and word lines each commonly connecting the other ends of plural cells arranged along a second direction; a read/write circuit formed on the substrate as underlying the cell arrays; first and second vertical wiring disposed on both sides of each cell array in the first direction to connect the bit lines to the read/write circuit; and third vertical wirings disposed on both sides of each cell array in the second direction to connect the word lines to the read/write circuit.
    Type: Grant
    Filed: August 25, 2011
    Date of Patent: August 7, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • RESISTANCE-CHANGING MEMORY DEVICE
    Publication number: 20120195101
    Abstract: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
    Type: Application
    Filed: April 13, 2012
    Publication date: August 2, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Haruki TODA
  • MEMORY SYSTEM AND MEMORY CONTROLLER
    Publication number: 20120151123
    Abstract: A memory system according to the embodiment comprises a memory device including plural memory cells capable of storing d bits of data and operative to read/write data at every page; and a memory controller operative to control the memory device. The memory controller includes a page buffer operative to hold page data to be read from/written in a page of the memory device and send/receive the page data to/from the memory device, a data processing unit operative to detect and correct an error in the page data by processing target data in a finite field Zp modulo p generated based on the page data (p is a prime that satisfies 2<p<2d), and a mapping unit operative to execute mapping of the target data from the data processing unit as page data within the page buffer.
    Type: Application
    Filed: September 20, 2011
    Publication date: June 14, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Semiconductor memory device
    Patent number: 8201055
    Abstract: A memory device includes an error detection and correction system with an error correcting code over GF(2n), wherein the system has an operation circuit configured to execute addition/subtraction with modulo 2n?1, and wherein the operation circuit has a first operation part for performing addition/subtraction with modulo M and a second operation part for performing addition/subtraction with modulo N (where, M and N are integers which are prime with each other as being obtained by factorizing 2n?1), and wherein the first and second operation parts perform addition/subtraction in parallel to output an operation result of the addition/subtraction with modulo 2n?1.
    Type: Grant
    Filed: April 5, 2011
    Date of Patent: June 12, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Resistance change memory device
    Patent number: 8194434
    Abstract: A resistance change memory device including: a cell array with memory cells arranged therein, the memory cell storing a resistance state as data in a non-volatile manner; a write buffer configured to supply voltage and current to a selected memory cell in accordance with data to be written in it; and a write control circuit configured to make a part of current supplied to the selected memory cell flow out in accordance with the selected memory cell's state change in a write mode.
    Type: Grant
    Filed: October 26, 2009
    Date of Patent: June 5, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Resistance change memory device and programming method thereof
    Patent number: 8184470
    Abstract: A method of programming a resistance change memory device includes: applying program voltage pulses to a memory cell for programming a target resistance value; setting thermal relaxation times between the respective program voltage pulses; and controlling the shape of each the program voltage pulse in accordance with the present cell's resistance value determined by the preceding program voltage pulse application.
    Type: Grant
    Filed: June 25, 2008
    Date of Patent: May 22, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Haruki Toda, Hiroto Nakai
  • Resistance-changing memory device
    Patent number: 8174864
    Abstract: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: May 8, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • THREE DIMENSIONAL PROGRAMMABLE RESISTANCE MEMORY DEVICE WITH A READ/WRITE CIRCUIT STACKED UNDER A MEMORY CELL ARRAY
    Publication number: 20120099365
    Abstract: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.
    Type: Application
    Filed: December 29, 2011
    Publication date: April 26, 2012
    Applicant: KABUSHHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • PHASE CHANGE MEMORY DEVICE
    Publication number: 20120099370
    Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
    Type: Application
    Filed: December 28, 2011
    Publication date: April 26, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki Toda
  • MEMORY SYSTEM
    Publication number: 20120079331
    Abstract: A memory system according to the embodiment comprises a cell array including cell units having p or more physical quantity levels (p is a prime of 3 or more); a code generator unit operative to convert binary-represented input data to a write code represented by elements in Zp that is a residue field modulo p; and a code write unit operative to write the write code in the cell unit in accordance with the association of the elements in Zp to different physical quantity levels, wherein the input data is recorded in (p?1) cell units, the (p?1) cell units including no cell unit that applies the same physical quantity level for write in the case where the input data is 0 and for write in the case where only 1 bit is 1.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • MEMORY SYSTEM
    Publication number: 20120075940
    Abstract: A memory system according to the embodiment comprises a cell array including word lines and plural memory cells operative to store data in accordance with plural different physical levels when selected by the word lines; a register operative to hold first data input from external; and a data converter unit operative to convert the first data held in the register into second data and overwrite the second data in the area of the register for holding the first data, and further operative to convert the second data held in the register into third data to be recorded in the memory cells and overwrite the third data in the area of the register for holding the second data.
    Type: Application
    Filed: September 14, 2011
    Publication date: March 29, 2012
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Haruki TODA
  • Resistance-changing memory device
    Patent number: 8107277
    Abstract: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.
    Type: Grant
    Filed: September 18, 2008
    Date of Patent: January 31, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Three-dimensional programmable resistance memory device with a read/write circuit stacked under a memory cell array
    Patent number: 8102697
    Abstract: A programmable resistance memory device includes a semiconductor substrate, at least one cell array, in which memory cells are arranged formed above the semiconductor substrate. Each of the memory cells has a stack structure of a programmable resistance element and an access element, the programmable resistance element storing a high resistance state or a low resistance state determined due to the polarity of voltage application in a non-volatile manner. The access element has such a resistance value in an off-state in a certain voltage range that is ten time or more as high as that in a select state. A read/write circuit is formed on a semiconductor substrate as underlying the cell array for data reading and data writing in communication with the cell array.
    Type: Grant
    Filed: October 1, 2010
    Date of Patent: January 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda
  • Phase change memory device
    Patent number: 8102699
    Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.
    Type: Grant
    Filed: December 13, 2010
    Date of Patent: January 24, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Haruki Toda