Abstract: According to an embodiment, a semiconductor memory device has: a memory cell array formed by stacking through insulation layers a plurality of memory mats which each have a plurality of first lines, a plurality of second lines and a plurality of resistance varying memory cells provided at intersection portions of the pluralities of first lines and second lines; and an accessing circuit which applies voltages to the memory cell array. A number of the first lines included in the memory mat is greater than a number of the second lines. When the accessing circuit accesses the selected memory cell, the accessing circuit selects a plurality of first lines and a second line connected to selected memory cells to which the accessing circuit needs to be connected and judges data stored in the selected memory cells according to currents flowing to the selected memory cells.

Abstract: A semiconductor memory device including a memory cell array including a memory cell layer containing plural memory cells operative to store data in accordance with different resistance states; and an access circuit operative to make access to the memory cells, the memory cell changing the resistance state from a first resistance state to a second resistance state on application of a voltage of a first polarity, and changing the resistance state from the second resistance state to the first resistance state on application of a voltage of a second polarity, the access circuit applying voltages, required for access to the memory cell, to first and second lines connected to a selected memory cell, and bringing at least one of the first and second lines connected to non-selected memory cells into the floating state to make access to the selected memory cell.

Abstract: A memory system according to the embodiment comprises a cell array including word lines and plural memory cells operative to store data in accordance with plural different physical levels when selected by the word lines; a register operative to hold first data input from external; and a data converter unit operative to convert the first data held in the register into second data and overwrite the second data in the area of the register for holding the first data, and further operative to convert the second data held in the register into third data to be recorded in the memory cells and overwrite the third data in the area of the register for holding the second data.

Abstract: An absorbent article ensuring that even when excreted urine diffuses by running down the wearer's skin, the urine is prevented from leaking out of the absorbent article. The absorbent article comprises an absorbent sheet that has at least one absorbent polymer-existing region in which the absorbent polymer is sandwiched by at least one liquid-pervious sheet and at least one absorbent polymer-nonexisting region which is free of absorbent polymer. The at least a part of the absorbent sheet is disposed in a rear waist region, and a planar shape of the absorbent polymer-existing region disposed on the rear waist region side of the longitudinal center of the crotch region of the absorbent sheet is a nearly V-shaped with an apex facing in the direction from the front waist region to the rear waist region in the longitudinal direction of the absorbent article.

Abstract: A memory device includes a substrate and a plurality of cell arrays stacked above the substrate. The cell arrays have bit lines coupled to first ends of memory cells and word lines coupled to the other ends. Each of the memory cells includes a variable resistance element to be set at a resistance value. While a selected bit line is set at a certain potential, word lines coupled to different memory cells, which are coupled in common to the selected bit line, are sequentially driven, so that different memory cells are accessed in a time-divisional mode.

Abstract: According to an embodiment, a semiconductor memory device comprises: a memory cell array configured having a plurality of memory cell mats, the memory cell mats including a plurality of first lines, second lines, and memory cells, and the memory cell mats being stacked such that the first and second lines are shared alternately by each of the memory cell mats; and a peripheral circuit. Each of the memory cells has a variable resistance characteristic and a current rectifying characteristic. An orientation from an anode toward a cathode of all the memory cells is identical. The peripheral circuit applies to one of the first line and the second line connected to an anode side of the selected memory cell a selected bit line voltage, and applies to the other a selected word line voltage.

Abstract: An absorbent article which has in a longitudinal direction from the front side to the rear side a front waist region, a rear waist region and a crotch region located between the front and rear waist regions. An absorbent sheet is provided between a topsheet and a second sheet which includes at least one liquid-pervious sheet having sandwiched therein an absorbent polymer that is present between a topsheet and a second sheet. The second sheet has a higher liquid diffusibility than the topsheet, the topsheet, a backsheet, an absorption body and the second sheet are disposed across the front waist region, the crotch region and the rear waist region, and the absorbent sheet is disposed in at least a part of the rear waist region.

Abstract: A resistance change memory device includes: a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.

Abstract: An absorbent article configured to ensure that even when the excreted urine diffuses by running down the wearer's skin, the skin is prevented from remaining wetted. In the absorbent article of the present invention, when an artificial urine is dropped and absorbed in the urination region of the crotch region, where an absorbent sheet is not disposed, the return amount of the artificial urine in the buttock region of the rear waist region, where an absorbent sheet is disposed, takes a value of 200 times less than the return amount of the artificial urine in the urination region; and the return amount of the artificial urine in the buttock region when the artificial urine is dropped and absorbed in the buttock region takes a value of 0.7 or less of the return amount of the artificial urine in the urination region when the artificial urine is dropped and absorbed in the urination region.

Abstract: A semiconductor memory device according to the embodiment comprises memory cells each having asymmetrical voltage-current characteristics, wherein the memory cell has a first state, and a second state and a third state of higher resistances than that in the first state, wherein the memory cell, (1) in the second state, makes a transition to the first state on application of a first voltage of the first polarity, (2) in the first state, makes a transition to the second state on application of a second voltage of the second polarity, (3) in the first state, makes a transition to the third state on application of a third voltage of the second polarity (the third voltage<the second voltage), and (4) in the third state, makes a transition to the first state on application of a fourth voltage of the first polarity (the fourth voltage<the first voltage).

Abstract: An error detection and correction system in accordance with an embodiment comprises: an encoding unit; a syndrome calculating unit; a syndrome element calculating unit; an error search unit; and an error correction unit, read and write of a memory cell array being assumed to be performed concurrently for m bits, and error detection and correction being assumed to be performed in data units of M bits (where M is an integer multiple of m), and an encoding unit and a syndrome calculating unit sharing a time-division decoder for performing data bit selection according to respective tables of check bit generation and syndrome generation, the time-division decoder being operative to repeat multiple cycles of m bit concurrent data input.

Abstract: A memory system according to the embodiment comprises a p-adic number converter unit operative to convert ?-digit, h-bit symbols to a k-digit, p-adic data word (p is a prime of 3 or more); an encoder unit operative to generate, from the p-adic data word, a code C composed of a residual field Zp of the prime p; a memory unit operative to store the code C as write data; an error correcting unit operative to apply an operation using a syndrome S generated from read data Y for error correcting the read data Y to regenerate the code C; a decoder unit operative to reverse-convert the code C to regenerate the p-adic data word; and a binary converter unit operative to convert the data word to a binary number to regenerate the binary data D.

Abstract: A memory system including: a memory device; an ECC system installed in the memory device so as to generate a warning signal in case there are uncorrectable errors; an address generating circuit for generating internal addresses in place of bad area addresses in accordance with the waning signal, the progressing of the internal addresses being selected as to avoid address collision with the address progressing of the memory device at least at the beginning; and a CAM for storing the internal addresses as substitutive area addresses, the CAM being referred to at an access time of the memory device so as to generate the substitutive area addresses in place of the bad area addresses in accordance with the warning signal.

Abstract: A resistance change memory device includes: a memory cell array with memory cells arranged therein, the memory cell having a variable resistance element for storing a rewritable resistance value; a reference cell formed of the same memory cells as those set in a high resistance state in the memory cell array, the reference cell being trimmed with selection of the number of parallel-connected memory cells to have a reference current value used for detecting data in the memory cell array; and a sense amplifier configured to compare a cell current value of a memory cell selected in the memory cell array with the reference current value of the reference cell.

Abstract: A resistance change memory device including a cell array, in which memory cells are arranged, the memory cell being reversibly set in one of a first data state and a second data state defined in accordance with the difference of the resistance value, wherein the memory device has a data write mode including: a first write procedure for writing the first data in the cell array; and a second write procedure for writing the second data in the cell array.

Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

Abstract: A disposable wearing article has a skin-contactable sheet moveable relative to a chassis. The chassis includes an inner sheet, an outer sheet and a liquid-absorbent panel interposed between these inner and outer sheets. The absorbent panel lies at least in the crotch region and extends into the front and rear waist regions in the longitudinal direction. In the rear waist region, a skin-contactable sheet adapted to come in contact with the wearer's skin is attached to the inner surface of the inner sheet. The skin-contactable sheet has front and rear ends extending in the transverse direction and lateral portions extending in the longitudinal direction and only the lateral portions are bonded to the inner sheet.

Abstract: A disposable wearing article improved so that a pressure put on the wearer's body may be partially alleviated. A disposable urine absorbent pad as one example of the disposable wearing articles has an inner sheet, an outer sheet and a liquid-absorbent structure interposed between these sheets. The liquid-absorbent structure is formed on an absorbent surface thereof with a pair of first raised portions protruding to the side of the inner sheet. The first raised portions lie in the rear waist region and extend in a longitudinal direction along lateral edges of the liquid-absorbent structure. The first raised portions may be formed of the same material as a core of the liquid-absorbent structure, specifically, of a mixture of fluff pulp and superabsorbent polymer particles.

Abstract: A phase-change memory device has a plurality of first wiring lines WL extending in parallel to each other, a plurality of second wiring lines BL which are disposed to cross the first wiring lines WL while being separated or isolated therefrom, and memory cells MC which are disposed at respective cross points of the first wiring lines WL and the second wiring lines BL and each of which has one end connected to a first wiring line WL and the other end connected to a second wiring line BL. The memory cell MC has a variable resistive element VR which stores as information a resistance value determined due to phase change between crystalline and amorphous states thereof, and a Schottky diode SD which is connected in series to the variable resistive element VR.

Abstract: A resistance-changing memory device has a cell array having memory cells, each of which stores as data a reversibly settable resistance value, a sense amplifier for reading data from a selected memory cell in the cell array, and a voltage generator circuit which generates, after having read data of the selected memory cell, a voltage pulse for convergence of a resistive state of this selected memory cell in accordance with the read data.