Abstract: A protection device includes a measurement device and a downstream evaluation device. The evaluation device is a unit for early short-circuit identification which actuates a semiconductor switch, which is preferably produced based on silicon carbide. The unit for early short-circuit identification preferably operates with switching thresholds which can be predetermined for the product of the current and the current rate of change, or on the basis of tolerant locus curves. In the latter case, different power factors (0.1<cos100 <0.9) are used in the locus curves in a locus curve representation of the current and current rate of change. The semiconductor switch preferably contains two back-to-back series-connected switching elements based on silicon carbide.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: A switching device for switching at a high operating voltage includes an LV switching element and a first HV switching element that are connected together in a cascode circuit. Furthermore, at least a second HV switching element is connected in series with the first HV switching element. A first protection element is connected between the HV grid terminals of the first and second HV switching elements, respectively.

Abstract: A method and an apparatus for turning off a cascode circuit comprising a series circuit formed by a low-blocking-capability and high-blocking-capability semiconductor switch, are described. When a turn-off command arrives, the gate voltage of the low-blocking-capability semiconductor switch is controlled in such a way that its drain voltage is held constant in the active range of the low-blocking-capability semiconductor switch. Consequently, an impermissible overvoltage at high potential of the cascode circuit at low potential is detected and actively limited.

Abstract: A semiconductor configuration for current control has an n-type first semiconductor region with a first surface, a p-type covered island region, within the first semiconductor region, with a second surface, an n-type contact region arranged on the second surface within the island region and a lateral channel region, formed between the first and second surface as part of the first semiconductor region. The channel is part of a current path from or to the contact region. The current within the lateral channel region may be influenced by at least one depletion zone. A lateral edge of the lateral channel region extends as far as the contact region.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.

Abstract: A hybrid power MOSFET, comprising a MOSFET and a junction FET, the MOSFET and the junction FET being electrically connected in series is disclosed. In accordance with the present invention, the hybrid power MOSFET is provided with a device for reducing the change in the gate voltage of the junction FET. Thus, a hybrid power MOSFET is obtained in which high over-voltages no longer arise and whose EMC response is much improved.

Abstract: The semiconductor configuration is formed with a lateral channel region and an adjoining vertical channel region in an n-conductive first semiconductor region. When a predetermined saturation current is exceeded, the lateral channel region is pinched off and the current is limited to a value below the saturation current.

Abstract: A silicon-based semiconductor component includes a high-efficiency barrier junction termination. In the semiconductor component, a silicon semiconductor region takes on the depletion region of an active area of the semiconductor component. The junction termination for the active area is formed with silicon with a doping that is opposite to that of the semiconductor region, and the junction termination surrounds the active area on or in a surface of the semiconductor region. The junction termination is doped with a dopant that has a low impurity energy level of at least 0.1 eV in silicon. Preferably Be, Zn, Ni, Co, Mg, Sn or In are used as acceptors and S, Se or Ti are provided as donors.

Abstract: A semiconductor product is described that contains a semiconducting body doped with a first conductivity type, a Schottky contact layer disposed on the semiconducting body and forms a Schottky contact with the semiconducting body, an ohmic contact layer disposed adjacent the Schottky contact layer, and a diode structure disposed laterally beside the Schottky contact. The diode structure has a first region disposed in the semiconducting body. The first region is doped with a second conductivity type and is connected to the Schottky contact layer through the ohmic contact layer. The diode structure has a second region functioning as part of an edge termination and surrounds the Schottky contact and the first region. The second region is disposed in the semiconducting body and is doped with the second conductivity type.

Abstract: The invention provides a method by which losses are reduced during the commutation of a free-running, driven power converter valve (T2) of an invertor phase (2) to a current-accepting power converter valve (T1) of said invertor phase (2). The current-accepting power converter valve (T1) is switched on at the beginning of the commutation process and the free-running, driven power converter valve (T2) is rapidly switched off as soon as the value of its drain voltage (UD) is zero.

Abstract: A semiconductor device contains a lateral power element. The power element is provided within a semiconductor layer formed of a semiconductor material having an energy gap of at least 2 eV and is laterally bounded by a trench in the semiconductor layer. The semiconductor layer is provided on a substrate having a thermal conductivity greater than that of silicon and is electrically insulated from a substrate surface remote from the semiconductor layer. This results in an integratable semiconductor device having a high reverse voltage and a high switching frequency.

Abstract: The power semiconductor components in prior art high-voltage smart power ICs frequently take up more than half of the total chip surface. To be able to produce the ICs more economically, the material consumption must be reduced, and hence, in particular, the surfaces of the drift zones of the power semiconductor components must be made significantly smaller. Based on the premise that the electrical breakdown field strength of silicon carbide is approximately ten times higher than that of silicon, the parts of a semiconductor component which receive voltage are integrated in silicon carbide. The drift zone can be made much smaller for the same reverse voltage. In an SiC MOS transistor with lateral current conduction, the SiC layer, which is only approximately 1-2 &mgr;m thick and is covered by an SiO2 layer, is arranged so as to be dielectrically insulated on an Si substrate. Two n+-doped SiC regions are used as source and drain contacts.

Abstract: An electronic switching device includes at least one first and one second semiconductor component, with a first anode connection and a second cathode connection being short-circuited. A control voltage that can be applied to a first grid connection is also at least partially present at a second grid connection. This reduces the forward resistance of the electronic switching device in the switched-on state.

Abstract: A lateral silicon carbide junction field effect transistor has p-conductive and n-conductive silicon carbide layers. The layers are provided in pairs in lateral direction in a silicon carbide body. Trenches for a source, a drain and a gate extend from a principal surface of the silicon carbide body and penetrate the layers. The source and drain trenches are filled with silicon carbide of one conductivity type, whereas the trench for the gate is filled with silicon carbide of a conductivity type that is different from the source and the drain.

Abstract: J-FET having a first semiconductor region (2, 3), which comprises a first contact (7) with a highly doped contact layer (8) serving as a source disposed between two second contacts (9) serving as a gate on its first surface (4). The three contacts (7, 9) are each connected to a respective second semiconductor region (5, 6). The first and second semiconductor regions (2, 3, 5, 6) are of opposite conductivity types. The second semiconductor regions (5) connected to the second contacts (9) extend in the first semiconductor region (2, 3) below the second semiconductor region (6) that is connected to the first contact (7), with the result that the three second semiconductor regions (5, 6) at least partially overlap in a projection onto a horizontal plane and a channel region (11) is formed between the three second semiconductor regions (5, 6) in the first semiconductor region (2, 3).

Abstract: A junction field-effect transistor containing a semiconductor region with an inner region is described. In addition, a first and a second connecting region, respectively, are disposed within the semiconductor region. The first connecting region has the same conductivity type as the inner region, but in a higher doping concentration. The second connecting region has the opposite conductivity type to that of the inner region. This reduces the forward resistance while at the same time maintaining a high reverse voltage strength.

Abstract: A method and an apparatus for balancing the power loss in at least two electrically parallel-connected cascode circuits, which each have a low-blocking semiconductor switch composed of silicon and a high-blocking-capability semiconductor switch composed of silicon carbide is disclosed. According to the present invention, an output voltage of each low-blocking-capability semiconductor switch is detected, with correction values being established as a function of them, and being superimposed on corresponding control signals for the low-blocking-capability semiconductor switches. An unbalanced current distributor can thus be actively balanced.

Abstract: A hybrid power MOSFET having a low blocking-capability MOSFET and a high blocking-capability junction FET is disclosed. In accordance with the present invention, this cascode circuit has at least two high blocking-capability junction FETs which are electrically connected in parallel and whose gate connections are respectively electrically conductively connected to the source connection of the low blocking-capability MOSFET by means of a connecting line. Thus, a hybrid power MOSFET for a high current-carrying capacity is obtained whose design technology has been considerably simplified on account of the use of only one control line and n+1 chips.