Abstract: An integrated circuit with electrostatic discharge protection includes a first transistor with a source terminal, a drain terminal and a gate terminal, and a second transistor with a source terminal, a drain terminal and a gate terminal. The gate terminal for each of the first and second transistors is connected to the drain terminal. The first transistor is connected in series with the second transistor by one of the drain and source terminals of the first transistor being connected to one of the drain and source terminals of the second transistor. The series circuit formed by the transistors is connected to an input terminal of the integrated circuit or to a supply terminal and a terminal that applies the reference potential of the integrated circuit. The series circuit of the transistors is dimensioned by the number of transistors and the setting of the channel length and channel width ratios of the transistors.

Abstract: The invention relates to a semiconductor memory device, a system with a semiconductor memory device, and a method for operating a semiconductor memory device, comprising the steps of reading out a data value, in particular a CAS latency time data value (CL) stored in a memory; activating or deactivating a device provided on said semiconductor memory device in support of a high speed operation, as a function of the data value (CL) stored.

Abstract: An apparatus for measurement of the thickness of thin layers by means of X-rays using an X-ray tube which emits X-rays which are directed at a layer to be measured, has at least one aperture apparatus arranged between the X-ray tube and the layer to be measured. The apparatus includes an area absorbing X-rays and an aperture opening. At least one aperture opening in the aperture apparatus has a geometric shape which, seen in the beam direction, projects an area which at least in places is matched to the geometry of the layer to be measured.

Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.

Abstract: A prestage for generating a control signal for an output driver of an integrated circuit, wherein the integrated circuit can be provided with a reference potential and a supply potential fixed in relation to the reference potential, comprises an input for receiving an input signal from the integrated circuit, a circuitry for generating an output signal based on the received input signal, an output for outputting the generated output signals as control signal for an output driver as well as a current source, which is effectively connected to the circuitry. Thereby, the circuitry for generating an output signal and the current source are connected in series and connected to a first potential and a second potential such that a prestage potential difference across the series circuit is higher than a supply potential difference between the supply potential and the reference potential.

Abstract: An apparatus for aging a chip, comprising a first bit line connected to a first memory cell; a second bit line connected to a second memory cell; an access circuit for accessing the first memory cell via the first bit line and for accessing the second memory cell via the second bit line; a first controller for selectively connecting/disconnecting the first bit line to the access circuit and from the access circuit, respectively; a second controller for selectively connecting/disconnecting the second bit line to the access circuit and from the access circuit, respectively; a normal operating mode controller for controlling the first and second controller, wherein the normal operating mode controller is formed such to select the first controller in a normal operating mode for accessing the first memory cell, and to connect the access circuit to the first bit line, while the second controller is controlled to disconnect the access circuit from the second bit line; wherein the apparatus comprises: an aging mode c

Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material.

Abstract: A decoding device includes a final decoder having at least one field-controlled semiconductor switching device. A transmission signal has a characteristic curve such that, in the event of an inactivation of the field-controlled semiconductor switching device, it is substantially completely blocked for transmission of a transmission signal by applying the transmission signal to the semiconductor switching device. Thus a particularly reliable operation of the decoding device is achieved.

Abstract: The invention relates to a method for reducing the current consumption of an electronic circuit having at least one test module for testing the electronic circuit. The test module is connected to at least one line and/or a connection of the electronic circuit. A test control signal is generated, by means of which the test module is at least partially decoupled from the line or the connection in an operating mode of the electronic circuit such that switching currents are prevented in the test module.

Abstract: The present invention relates to an input circuit for receiving an input signal in an integrated circuit, having a differential amplifier whose first input can have a predetermined reference voltage applied to it and whose second input can have the input signal applied to it, and having a current source for operating the differential amplifier at its operating point, wherein a setting circuit is connected to the current source in order to set the operating point of the differential amplifier in an optimum manner on the basis of the predetermined reference voltage.

Abstract: A semiconductor memory includes: at least two memory banks that each have a memory cell matrix, an address decoding unit which includes a bank address decoding unit, a row address decoding unit and a column address decoding unit. At least one demultiplexer is connected upstream of the address buffer memories provided in the row address decoding unit and/or in the column address decoding unit. This demultiplexer is connected to the bank address decoder in order, on the basis of the decoded bank address, to activate the corresponding address buffer memory.

Abstract: An integrated circuit has a voltage divider that is configured to save current. The circuit includes a capacitor that is inventively connected to a potential sink or potential source by way of a charge branch even when the voltage divider is inactive. The capacitor is thus held at a charge state that corresponds to the charge state given an active voltage divider. The voltage divider thus becomes functional in a shorter time following activation, because the capacitor does not require recharging.

Abstract: A RAM memory circuit has at least one memory bank with a multiplicity of memory cells arranged like a matrix in rows and columns and is subdivided into q?2 areas, each of which comprises p?1 segments each comprising a plurality of columns. Each segment is assigned a bundle of master data lines, which branches from an area bus assigned to the relevant area and, for its part, branches via a switching network to the memory cells of the relevant segment. The area buses can be connected cyclically to a common data port. In order to allow a read operation the beginning of which overlaps the end of a preceding write operation, each master data line bundle has coupled to it a data latch for holding the data respectively appearing there, and an isolating switch is in each case provided between each master data line bundle and the assigned area bus.

Abstract: In a semiconductor memory, there is capacitive coupling between bit lines that largely run in parallel. Outer sections of the bit lines are connected via respective switches to a sense amplifier arranged between the switches. When a memory cell is being read, the capacitive interference by other bit lines that are not coupled to the memory cell being read is kept as low as possible before the start of amplification by the sense amplifier by turning on the switches in that bit line. During the amplification phase, the remote outer section of that bit line is disconnected using the appropriate switch. In one embodiment, the capacitance of the bit line that is not connected to the memory cell to be read is increased further by additionally activating a precharging circuit.

Abstract: One embodiment of the invention provides a method for producing an integrated memory module containing a command decoding device that responds to external operation commands to set operating states of the memory module for carrying out operations in accordance with a predetermined specification of the memory module. The command decoding device is formed with a decision memory containing memory locations Mi,j, the storage capacity of which suffices to receive, for an arbitrary specification from a plurality of different specifications, a decision information item specifying whether or how the second operation command of selected pairs of two directly successive operation commands is to be executed. After integration of the command decoding device thus formed, the decision information items demanded in the case of the predetermined specification are written to the memory locations of the decision memory.

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

Abstract: An RC network is integrated in a semiconductor circuit chip and is connected between an input pad or pin and a ground node coupled to a substrate of the chip. The RC network has a plurality of resistance elements, a plurality of capacitance elements and a plurality of connection/isolation elements, which are provided in each case between at least one of the resistance elements and the individual capacitive elements. The inventive circuit configuration enables an optional and independent setting of the input capacitance and of the input resistance of the semiconductor circuit chip, depending on the connection/isolation state of the connection/isolation elements.

Abstract: An ESD protection apparatus for limiting a voltage superimposed on an electric useful voltage to an allowable voltage, comprising a plurality of series-connected diodes. The diodes are forward-biased with reference to the useful voltage. Each individual forward-biased diode has a threshold voltage. The sum of the threshold voltages of the series-connected diodes corresponds to the allowable voltage.

Abstract: A method for writing and reading data is performed on a dynamic memory circuit. The memory circuit has memory cells that can be addressed via word lines and bit lines. A word line is activated in the event of addressing of a memory area with a specific address. A word line has a plurality of mutually separate word line sections. Via the bit lines, in the event of addressing with the specific address, in parallel, a first number of data can be written to memory cells addressed by the address or the first number of data can be read from memory cells addressed by the address. In the event of addressing with a specific address, only a portion of the word line sections are activated, in order that only a portion of the memory cells connected to the word line are written to in parallel or read from in parallel.