Abstract: In the method for modifying a default time duration between an execution instant of a second operation and an earlier execution instant of a first operation executed earlier in a memory element, wherein the memory element is operable in a test operation mode and a normal operation mode, at first a real time duration in the memory element is determined and provided during the test operation mode, wherein the real time duration is chosen so that a performance parameter of the memory element, when using the real time duration between the execution instants of the first and second operations, improves over a situation in which the default time duration between the execution instants of the first and second operations is used. Then, the default time duration is changed in direction of the real time duration during the test operation mode to obtain a modified default time duration.

Abstract: A method for fabricating at least one mesa or ridge structure in a layer or layer sequence, in which a sacrificial layer (4) is applied and patterned above the layer or layer sequence. A mask layer is applied and patterned above the sacrificial layer for definition of the mesa or ridge dimensions. The sacrificial layer (4) and of the layer or layer sequence are removed so that the mesa or ridge structure is formed in the layer or layer sequence. A part of the sacrificial layer (4) is selectively removed from the side areas thereof which have been uncovered in the previous step, so that a sacrificial layer remains which is narrower in comparison with a layer that has remained above the sacrificial layer as seen from the layer or layer sequence. A coating is applied at least to the sidewalls of the structure produced in the previous steps so that the side areas of the residual sacrificial layer are not completely overformed by the coating material.

Abstract: An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

Abstract: A component carrier for holding at least one component (12), in particular for surface coating by electrodeposition, having at least one holding magnet (31), the magnetic field lines of which run through the component (12) in a region close to a contact surface (36), having a diaphragm (16), which accommodates the at least one component (12) in a holding position (38) with respect to the at least one holding magnet (31) on at least one contact surface (36) of an electrically conductive housing (14), the pole axis of the at least one holding magnet (31) being positioned transversely with respect to the contact surface (36), in which component carrier a resulting magnetic holding force which acts on the at least one component (12) in the holding position (38) can be reduced by displacement of the at least one holding magnet (36) out of the holding position (38) or by displacement of the at least one component (12) out of the holding position (38) or by a relative movement of the at least one component (12) and

Abstract: A data memory circuit is provided. In one embodiment, the data memory circuit comprises a plurality of addressable memory cells, a command decoding device for decoding external commands and a control device for controlling or initiating operations for the operation of the data memory circuit in each case in a manner dependent on the decoded commands. The memory circuit has critical operating states in which the execution of specific commands is impermissible resulting in the course of specific operations in the data memory circuit, wherein a command buffer device buffer-stores commands received during the duration of their impermissibility and releases them for execution after the end of their impermissibility.

Abstract: A RAM memory circuit and method for controlling the same includes memory cells disposed in a matrix of rows and columns each addressed for writing in/reading out a datum by activation of a word line assigned to a relevant row and connection of a sense amplifier assigned to a relevant column to a data path. A control device can be set by an immediate-write command, commanding the write operation, to initiate connection of the sense amplifiers selected by the column addresses provided to the data path at an instant ta+Tw, where ta is the instant of activation of the word line selected by a row address provided and Tw is less than a charging time Tc specific to the memory circuit and is necessary, starting from a word line activation, to transfer the datum stored in a memory cell of the relevant row to the respectively selected sense amplifier and amplify it there.

Abstract: Integrated circuits are tested on the wafer level through an additional circuit part that is electrically connected via at least one connecting line with the associated integrated circuit. The additional circuit part is integrated into an interspace between the integrated circuits of the wafer. Functions of the integrated circuit can be controlled via the connecting line. For example, in the case of a memory module such as a DRAM, internal voltages and/or currents of the integrated circuit can advantageously be measured even on internal lines which are otherwise only accessible with difficulty. Following the wafer-level testing and dicing of the integrated circuits into individual chips, the additional circuit part becomes unusable.

Abstract: An addressing device selects an element from a set of N≦2K regular elements or alternatively from a set of R<N redundant elements in dependence on a K-bit input address which is applied to a 1-out-of-N decoder, and which addresses the regular elements. For each redundant element, a bypass circuit is provided and has in each case a reference bit transmitter for supplying K reference bits that are programmable by selective destruction or by selective introduction of conductive links in order to set a comparison device to the identification of a selected address. If the relevant address is identified, the bypass circuit addresses the redundant element assigned to it while switching off the 1-out-of-N decoder, provided that it is sensitized. For its sensitization, each bi-stable-circuit checks M<K preselected specimens of the reference bits in order to set the relevant bypass circuit into an active state if the binary values of these reference bits differ from a chosen bit combination.

Abstract: In a memory element with a first number of memory cells having a first retention time for holding a content of the memory cells and a second number of memory cells having a second retention time for holding the content of the memory cell, a method for refreshing the memory cells comprises a step of refreshing the first number of memory cells when reaching the first retention time and a step of refreshing the second number of memory cells when reaching the second retention time. An apparatus for refreshing the memory cells of the memory element is provided for refreshing the first number of memory cells when reaching the first retention time, and for refreshing the second number of memory cells when reaching the second retention time.

Abstract: An apparatus for non-destructive measurement of the thickness of thin layers, has a housing and a probe which is connected to an evaluation unit and to which signals are emitted during a measurement for determining the layer thickness, and having a display apparatus which indicates at least the measurement data from the evaluation unit. At least one further display apparatus is positioned on the housing away from the plane of the first display apparatus.

Abstract: A method for the nondestructive measurement of the thickness of thin layers having a probe, having a first coil device on an inner core, the geometrical center of which coil device and the geometrical center of at least one second coil device coincide, the at least one second coil device partially surrounding the first coil device, and an evaluation unit, to which signals of the coil devices are emitted during a measurement for ascertaining the layer thickness. A circuit is provided, by which the first and the at least one second coil devices are excited sequentially during a measurement.

Abstract: A memory module has a memory cell configuration. For the purpose of testing the memory cell configuration, the memory module has a test structure with at least two test circuits, which are disposed in a distributed fashion on the memory module and are connected to one another via a common test switching bus, which can be connected to an address bus of the memory module via a decoupling circuit during a test operation.

Abstract: An integrated DRAM memory component has sense amplifiers which, respectively within the framework of the integrated component, are formed from a multiplicity of transistor structures, arranged regularly in cell arrays, and signal interconnect structures with amplification transistors for bit line signal amplification. The amplification transistors are of identical design and they lie opposite one another in pairs in adjacent transistor rows. Signal interconnects, which are associated with the transistor rows and run parallel thereto, supply actuation signals. The signal interconnects for the actuation signals have the same arrangement symmetry as the amplification transistors, which means that the amplification transistors in adjacent transistor rows are in the same signal interconnect proximity.

Abstract: A transistor configuration for a bandgap circuit is configured in the form of an npn transistor. An insulated p-type well, which is surrounded by a buried n-type well, is used as a base terminal. The n-type well constitutes the emitter terminal. A negatively doped region, which acts as a collector terminal, is formed in the p-type well. The structure that is used exists in DRAM processes, and it can therefore be used to form an npn transistor as a footprint diode in bandgap circuits.

Abstract: An apparatus for measurement of the thickness of thin layers by means of X-rays using an X-ray tube which emits X-rays which are directed at a layer to be measured, has at least one aperture apparatus arranged between the X-ray tube and the layer to be measured. The apparatus includes an area absorbing X-rays and an aperture opening. At least one aperture opening in the aperture apparatus has a geometric shape which, seen in the beam direction, projects an area which at least in places is matched to the geometry of the layer to be measured.

Abstract: A storage circuit comprises a first clock receiver circuit for receiving an external clock signal so as to produce from said external clock signal a first internal clock signal and so as to output the first internal clock signal for use within the storage circuit, as well as a second clock receiver circuit for receiving said external clock signal and for producing from said external clock signal a second internal clock signal, said second clock receiver circuit consuming less current than said first clock receiver circuit. In addition, a circuit block is provided, which operates on the basis of said first or second internal clock signal and which is used for switching off said first clock receiver circuit when a power-down-precharge mode exists, said circuit block operating on the basis of said second internal clock signal, when the first clock receiver circuit has been switched off. A reduced current consumption can be achieved by the present invention in this way.

Abstract: A dynamic semiconductor memory has memory cells disposed in a cell field. The memory cells are connected to master word lines by way of a word line driver for driving the memory cells. As a rule, all the master word lines that are located in the segmented cell field are inactive, with at most one master word line being active. The master word lines are switched to an active low state, and a portion of the master word lines in a region of the cell field are inverted by a control device located at the beginning of the cell field. The deactivated master word lines in the cell field are at a ground potential, which, in view of the large number of existing master word lines, advantageously substantially reduces the leakage current that must be applied by the generators.

Abstract: Data register for storage of a data bit with integrated signal level conversion. The data register has an input for application of a data bit input signal which has a first voltage shift between a reference ground potential and a first voltage potential, a controllable switching device for passing on the applied data bit signal, a potential isolating transistor having a control connection at the first voltage potential, a first inverter which emits, in inverted form, the passed-on data bit input signal as a data bit output signal having a second voltage shift between the reference ground potential and a second supply potential, at one output of the data register for further data processing, and a second inverter, which feeds back the data output signal for storage of the data bit.

Abstract: A semiconductor memory is described which has a clock input, a signal input, a data output, a measuring device, a control circuit, and a latency. The latency elapses between the activation of the signal input and the availability of the data to be read at the data output. A clock signal is fed to the clock input. On the basis of the clock signal, the measuring device determines a value for the latency and the control circuit configures the semiconductor memory with the determined value for the operation of the semiconductor memory.

Abstract: A digital memory circuit has at least two pairs of adjacent memory banks. Each of the banks has n parallel terminals for n read/write data lines. Each bank pair has only two bundles of n/2 read/write data lines. A first bundle is assigned to the first half of a first bank and to a second half of a second bank and the second bundle is assigned to a second half of the first bank and to a first half of the second bank. Data are input/output in parallel to n/2 input/output lines with the timing of successive half-periods of a clock signal. A changeover device is changeable between different switching states for connecting a bundle of n/2 input/output lines to the read/write data lines of the bank pair containing the addressed bank, depending on whether the data are assigned to the first or second half-period of the clock signal.