Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.

Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: A method of making a semiconductor device assembly is provided. The method comprises attaching a first semiconductor device to an upper surface of a substrate and disposing a stencil over the upper surface of the substrate. The stencil includes (i) an opening and (ii) a cavity in which the first semiconductor device is disposed. The method further comprises screen-printing an epoxy material into the opening and onto the upper surface of the substrate, removing the stencil, and planarizing an upper surface of the epoxy material to form an epoxy spacer.

Abstract: An apparatus includes a primary layer of a substrate. The apparatus includes a secondary layer of the substrate having a first open area that extends through the secondary layer to an inner layer of the substrate. The apparatus includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes first component bond pads that are disposed on the inner layer and that are exposed via the first open area of the secondary layer.

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second pair of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to first and second distances between electrical contacts of the first and second surface-mount capacitors.

Abstract: Substrates for semiconductor packages, including hybrid substrates for decoupling capacitors, and associated devices, systems, and methods are disclosed herein. In one embodiment, a substrate includes a first pair and a second of electrical contacts on a first surface of the substrate. The first pair of electrical contacts can be configured to receive a first surface-mount capacitor, and the second pair of electrical contacts can be configured to receive a second surface-mount capacitor. The first pair of electrical contacts can be spaced apart by a first space, and the second pair of electrical contacts can be spaced apart by a second space. The first and second spaces can correspond to corresponding to first and second distances between electrical contacts of first and second surface-mount capacitors.

Abstract: Semiconductor devices having multiple substrates and die stacks, and associated systems and methods, are disclosed herein. In some embodiments, a semiconductor device includes a package substrate, and a first die stack mounted on the package substrate and including a plurality of first memory dies. The device can include a substrate mounted on the first die stack, the substrate including a plurality of routing elements. The device can also include a second die stack mounted on the substrate, the second die stack including a plurality of second memory dies. The device can further include a controller die mounted on the substrate. The controller die can be configured to communicate with the second die stack via the routing elements of the substrate. The device can include a mold material encapsulating the first die stack, the second die stack, the substrate, and the controller die.

Abstract: A semiconductor device assembly includes a substrate, a first stack of semiconductor dies disposed directly over a first location on the substrate, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Abstract: Semiconductor devices and associated systems and methods are disclosed herein. In some embodiments, the semiconductor device is an assembly that includes a package substrate having a front side and a backside opposite the front side. A controller die with a first longitudinal footprint can be attached to the front side of the package substrate. A passive electrical component is also attached to the front side of the package substrate. A stack of semiconductor dies can be attached to the controller die and the passive electrical component. The stack of semiconductor dies has a second longitudinal footprint greater than the first longitudinal footprint in at least one dimension. The controller die and the passive electrical component are positioned at least partially within the second longitudinal footprint, thereby at least partially supporting the stack of semiconductor dies.

Abstract: An apparatus includes a substrate for mounting an integrated circuit. The substrate includes a primary layer including a first surface that is a first external surface of the substrate. The substrate includes an inner layer that is located below the primary layer and including a second surface. A portion of the second surface of the inner layer is exposed via an open area associated with the primary layer. The inner layer includes a first multiple of wire bond pads that are exposed via the open area associated with the primary layer.

Abstract: A semiconductor device assembly includes a substrate having a plurality of external connections, a first stack of semiconductor dies disposed directly over a first location on the substrate and electrically coupled to a first subset of the plurality of external connections, and a second stack of semiconductor dies disposed directly over a second location on the substrate and electrically coupled to a second subset of the plurality of external connections. A portion of the semiconductor dies of the second stack overlaps a portion of the semiconductor dies of the first stack. The semiconductor device assembly further includes an encapsulant at least partially encapsulating the substrate, the first stack and the second stack.

Abstract: An apparatus includes an integrated circuit and a substrate coupled to the integrated circuit. The substrate includes a primary layer having a first surface that is a first external surface of the substrate. The primary layer includes an open area that extends through the primary layer to an inner layer of the substrate. The substrate includes a secondary layer. The inner layer is located between the primary layer and the secondary layer. The inner layer includes a third surface that is orientated approximately parallel to the first surface of the primary layer. A portion of the third surface of the inner layer is exposed via the open area of the primary layer. A first plurality of wire bond pads are disposed on the portion of the third surface of the inner layer that is exposed via the open area of primary layer.

Abstract: An apparatus includes a primary layer of a substrate that includes an open area that extends through the primary layer to an inner layer of the substrate. The apparatus includes a secondary layer of the substrate. The apparatus also includes the inner layer of the substrate that is positioned between the primary layer and the secondary layer. The inner layer includes component bond pads that are disposed on the inner layer and that are exposed via the open area of the primary layer.