Patents by Inventor Hem P. Takiar

Hem P. Takiar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5969783
    Abstract: A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41;, 41") to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46', 46") extending from a distal end of the arm portion (45). Each finger portion (46, 46', 46") defines a coupling region (47, 47', 47") adapted to operably couple a respective imaging device (41, 41', 41") to a respective finger portion (46, 46', 46") for support thereof. The finger portions (46, 46', 46") are further adapted to strategically couple each respective imaging device (41, 41', 41") to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof. The terminals (66) supportively and communicably coupled to the bond pads (67) of the die (58) for support thereof.
    Type: Grant
    Filed: December 11, 1998
    Date of Patent: October 19, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Ranjan J. Mathew
  • Patent number: 5914528
    Abstract: A lead frame structure includes a lead frame skeleton and at least one die bar connected between the lead frame skeleton and a non-quadrangular die attach paddle. Each of a plurality of leads has an outer edge connected to the lead frame skeleton and an inner edge disposed adjacent to but separated from the periphery of the die attach paddle. Preferably, the inner edge of each lead is separated from the periphery of the die attach paddle by about 5-10 mils.
    Type: Grant
    Filed: April 28, 1997
    Date of Patent: June 22, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Kuan L. Chen
  • Patent number: 5901043
    Abstract: In semiconductor packaging, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die. A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
    Type: Grant
    Filed: August 3, 1994
    Date of Patent: May 4, 1999
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar
  • Patent number: 5783866
    Abstract: A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.
    Type: Grant
    Filed: May 17, 1996
    Date of Patent: July 21, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew, Hee Jhin Kim
  • Patent number: 5718038
    Abstract: An electronic assembly for connecting to an electronic system is disclosed which includes, in one embodiment, a connector having a group of contacts, each contact having a mating portion and an interconnect finger. A first circuitry module includes a group of leads providing a signal path to electronic components contained therewithin, wherein each of the leads is coupled directly to an interconnect finger of a corresponding one of the group of connector contacts. A protective body is rigidly coupled to the first connector and is formed to encase the first circuitry module and to provide support and protection to the circuitry module. In another embodiment suitable for a PCMCIA card assembly, each of a group of leads of a leaded chip-carrier module is directly connected to interconnect fingers of the connector.
    Type: Grant
    Filed: June 6, 1995
    Date of Patent: February 17, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Michael W. Patterson
  • Patent number: 5715594
    Abstract: A portable peripheral card for an electrical device is disclosed that has an injected molded housing package. In one aspect of the invention, the peripheral card has a printed circuit board, a female electrical connector, and a solid one-piece injected molded package. The printed circuit board has electrical components mounted thereon and the female electrical connector is attached to the printed circuit board to permit communications between the electrical components on the printed circuit board and the electrical device. The solid one-piece package encapsulates the printed circuit board and the electrical components yet exposes a portion of the electrical connector to facilitate electrical connections between the printed circuit board and the electrical device. In one preferred embodiment, the portable peripheral card is a PCMCIA card. Methods of manufacturing such peripheral cards are also disclosed.
    Type: Grant
    Filed: June 14, 1996
    Date of Patent: February 10, 1998
    Assignee: National Semiconductor Corporation
    Inventors: Michael W. Patterson, Hem P. Takiar
  • Patent number: 5629563
    Abstract: A multi-chip packaging arrangement that contemplates stacking discrete components over film based components is disclosed. The multi-chip package includes a substrate having one or more film based components formed thereon. A discrete component is mounted on the substrate over the film based component such that it is electrically isolated from the film based component. One or more die components are also mounted on the substrate and a plurality of leads are provided for electrically connecting the multi-chip package to external circuitry. Wiring traces formed on the substrate are provided to electrically connect various ones of the components and the leads. A packaging material is provided to encapsulate the components and the wiring traces and leaves a portion of the leads exposed to facilitate electrically connecting the multi-chip package to external circuitry. Methods of making such multi-chip packages are also disclosed.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: May 13, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Uli H. Hegel, Peter H. Spalding, James L. Crozier, Michelle M. Hou-Chang, Martin A. Delateur
  • Patent number: 5625235
    Abstract: Multichip integrated circuit modules having crossed bonding wires are disclosed together with methods of making the same. The integrated circuit dies of the multi-chip modules are affixed to a suitable die supporting substrate. The dies are then electrically coupled to each other and/or to associated lead traces by wire bonding the dies, with at least two of the bonding wires being crossed. The integrated circuit dies, the bonding wires, and at least a portion of the lead traces are enclosed in a package. In one embodiment, the bonding wires used in the wire bonding step are precoated with an insulating material. In another embodiment, the insulating layers are formed on the bonding wires after the wire bonding step to prevent shorting between the wires. The insulating layers may be formed in a variety of manners. By way of example, the wires can be oxidized, or they may be coated with a protective material.
    Type: Grant
    Filed: June 15, 1995
    Date of Patent: April 29, 1997
    Assignee: National Semiconductor Corporation
    Inventor: Hem P. Takiar
  • Patent number: 5617297
    Abstract: A portable peripheral card for an electrical device is disclosed that has an injected molded housing package. In one aspect of the invention, the peripheral card has a printed circuit board, a female electrical connector, and a solid one-piece injected molded package, whereas the molding compound includes organic polymer fibers. The printed circuit board has electrical components mounted thereon and the female electrical connector is attached to the printed circuit board to permit communications between the electrical components on the printed circuit board and the electrical device. The solid one-piece package encapsulates the printed circuit board and the electrical components yet exposes a portion of the electrical connector to facilitate electrical connections between the printed circuit board and the electrical device. In one preferred embodiment, the organic polymer fibers includes at least one selected from the group consisting of cotton, cellulose, polyester and nylon.
    Type: Grant
    Filed: September 25, 1995
    Date of Patent: April 1, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Randy Lo, Hem P. Takiar
  • Patent number: 5596225
    Abstract: A leadframe for use in an integrated circuit package including at least one integrated circuit die attached to the leadframe and an encapsulant material surrounding the die and portions of the leadframe is herein disclosed. The leadframe includes a central portion having a plurality of perforations through the central portion adapted to allow the flow of the encapsulant material through the perforations during the molding process of the manufacture of the integrated circuit package thereby (i) preventing the flow of the encapsulant material from shifting the die attach pad during the manufacture of the package and (ii) providing anchoring for the encapsulant material to the leadframe to prevent delamination and cracking of the package.
    Type: Grant
    Filed: March 27, 1996
    Date of Patent: January 21, 1997
    Assignee: National Semiconductor Corporation
    Inventors: Ranjan J. Mathew, Hem P. Takiar
  • Patent number: 5554821
    Abstract: A portable peripheral card for an electrical device is disclosed that has an injected molded housing package. In one aspect of the invention, the peripheral card has a printed circuit board, a female electrical connector, and a solid one-piece injected molded package. The printed circuit board has electrical components mounted thereon and the female electrical connector is attached to the printed circuit board to permit communications between the electrical components on the printed circuit board and the electrical device. The solid one-piece package encapsulates the printed circuit board and the electrical components yet exposes a portion of the electrical connector to facilitate electrical connections between the printed circuit board and the electrical device. In one preferred embodiment, the portable peripheral card is a PCMCIA card.
    Type: Grant
    Filed: July 15, 1994
    Date of Patent: September 10, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Michael W. Patterson, Hem P. Takiar
  • Patent number: 5543640
    Abstract: A high capacity gate array which incorporates an effectively three dimensional interconnect network. The array is formed from multiple smaller arrays which are connected to a common substrate by means of flip-chip bonding. The substrate is typically a multi-layer substrate which has interconnect lines embedded on or within it, thereby allowing a set of desired interconnections between the smaller logic cell arrays to be implemented. The contact points for connecting logic cells or arrays of cells to the substrate result from placing a multitude of solder bumps on the smaller arrays of logic cells at desired interconnect points. Connecting the interconnect point solder bumps to the multi-layer substrate then permits the individual logic cell arrays to be interconnected in a desired manner. A three dimensional interconnect network is realized by interconnecting corresponding points on different logic cell arrays so that the arrays are connected in parallel.
    Type: Grant
    Filed: September 29, 1995
    Date of Patent: August 6, 1996
    Assignee: National Semiconductor Corporation
    Inventors: James Sutherland, Timothy L. Garverick, Hem P. Takiar, George F. Reyling, Jr.
  • Patent number: 5530622
    Abstract: An electronic assembly for connecting to an electronic system is disclosed which includes, in one embodiment, a connector having a group of contacts, each contact having a mating portion and an interconnect finger. A first circuitry module includes a group of leads providing a signal path to electronic components contained therewithin, wherein each of the leads is coupled directly to an interconnect finger of a corresponding one of the group of connector contacts. A protective body is rigidly coupled to the first connector and is formed to encase the first circuitry module and to provide support and protection to the circuitry module. In another embodiment suitable for a PCMCIA card assembly, each of a group of leads of a leaded chip-carrier module is directly connected to interconnect fingers of the connector.
    Type: Grant
    Filed: December 23, 1994
    Date of Patent: June 25, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Michael W. Patterson
  • Patent number: 5504370
    Abstract: An electronic system circuit package is disclosed herein. The package utilizes a lead frame having an electrically conductive component support segment incorporating provisions for mounting a plurality of electronic components directly on the support segment in accordance with a predetermined circuit design. The circuit package is then encapsulated in a dielectric medium. In a preferred embodiment, at least some of the electronic components are mounted directly to electrically isolated subsegments of the component support segment and electrically interconnected through their respective subsegments to other components.
    Type: Grant
    Filed: September 15, 1994
    Date of Patent: April 2, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar
  • Patent number: 5502289
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: March 13, 1995
    Date of Patent: March 26, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin
  • Patent number: 5495398
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: June 5, 1995
    Date of Patent: February 27, 1996
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin
  • Patent number: 5437095
    Abstract: A method of making an integrated circuit package is disclosed herein along with the package itself, which package is encapsulated by plastic that is caused to flow in a given direction during the package's formation. The package itself includes an IC chip having an army of chip output/input terminals, and means for supporting the chip including an array of electrically conductive leads, all of which are provided for connection with the output/input terminals of the IC chip. In addition, the overall package includes bonding wires connecting the chip output/input terminals with respective ones of the leads such that each bonding wire extends in a direction that defines an acute angle of less than 45 degrees with the given flow direction of the plastic material used to encapsulate the IC chip, support means and bonding wires. In a preferred embodiment, at least a portion and most preferably substantially all of the bonding wires are substantially parallel with the given flow direction of the plastic material.
    Type: Grant
    Filed: December 21, 1993
    Date of Patent: August 1, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Luu T. Nguyen, Hem P. Takiar
  • Patent number: 5428245
    Abstract: A lead frame for use in an integrated circuit package is disclosed herein. The lead frame includes a magnetic component winding wherein the winding is formed as an integral part of the lead frame. Additional windings may be formed as an integral part of the lead frame and then folded into position over the first winding to form a multiple layered magnetic component winding. In one embodiment, the lead frame based winding is coated with a magnetic material to form a lead frame based inductor. There is also disclosed a method of producing a lead frame including a magnetic component winding wherein the winding is formed as an integral part of the lead frame.
    Type: Grant
    Filed: May 6, 1994
    Date of Patent: June 27, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Seth R. Sanders, Hem P. Takiar
  • Patent number: 5422435
    Abstract: A circuit assembly which includes a semiconductor die having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on the first surface. A first element having substantially parallel opposing first and second surfaces and at least one electrical contact mounted on one of its surfaces is mounted on and at least partially supported at its second surface by the first surface of the semiconductor die. The first element is positioned such that the semiconductor die electrical contact is exposed. A fine wire conductor having first and second ends is connected at its first end to either the semiconductor die electrical contact or the first element electrical contact. A method of manufacturing this circuit assembly is also disclosed.
    Type: Grant
    Filed: May 22, 1992
    Date of Patent: June 6, 1995
    Assignee: National Semiconductor Corporation
    Inventors: Hem P. Takiar, Peng-Cheng Lin, Luu T. Nguyen
  • Patent number: 5339216
    Abstract: In semiconductor packing, a method and device for reducing thermal stress on a die and for reinforcing the strength of a die, A thermally-conductive member is positioned in a cooperating manner with the die during the packaging process.
    Type: Grant
    Filed: March 2, 1993
    Date of Patent: August 16, 1994
    Assignee: National Semiconductor Corporation
    Inventors: Peng-Cheng Lin, Hem P. Takiar