Patents by Inventor Hem P. Takiar
Hem P. Takiar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20040251523Abstract: Improved apparatus and methods for stacking integrated circuit packages having leads are disclosed. According to one embodiment, the leads of an integrated circuit package are exposed and provided with solder balls so that corresponding leads of another integrated circuit package being stacked thereon can be electrically connected. The stacking results in increased integrated circuit density with respect to a substrate, yet the stacked integrated circuit packages are able to still enjoy having an overall thin or low profile.Type: ApplicationFiled: June 16, 2003Publication date: December 16, 2004Applicant: SanDisk CorporationInventor: Hem P. Takiar
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Patent number: 6556269Abstract: A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41;, 41″) to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46′, 46″) extending from a distal end of the arm portion (45). Each finger portion (46, 46′, 46″) defines a coupling region (47, 47′, 47″) adapted to operably couple a respective imaging device (41, 41′, 41″) to a respective finger portion (46, 46′, 46″) for support thereof. The finger portions (46, 46′, 46″) are further adapted to strategically couple each respective imaging device (41, 41′, 41″) to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof.Type: GrantFiled: March 7, 2002Date of Patent: April 29, 2003Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Ranjan J. Mathew
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Patent number: 6521970Abstract: A wafer level fabricated chip scale integrated circuit package having an air gap formed between the integrated circuit die of the package and compliant leads located over and conductively attached to the die is described. Contact bumps offset on the compliant leads provide for connection of the integrated circuit package to other substrates. In some embodiments, the compliant leads include a conductive layer overlaid with an outer resilient layer, and may further include an inner resilient layer beneath the conductive layer. The outer resilient layer has a via formed through it exposing the underlying conductive layer. The via is offset along the compliant lead a horizontal distance from the bond pad to which the compliant lead is conductively coupled. The chip scale package provides a highly compliant connection between the die and any substrate that the die is attached to.Type: GrantFiled: September 1, 2000Date of Patent: February 18, 2003Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Nikhil Vishwanath Kelkar
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Patent number: 6459143Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: GrantFiled: April 26, 2001Date of Patent: October 1, 2002Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6448632Abstract: A semiconductor device comprising a mark located on a surface of the semiconductor device and a metal layer covering the marked surface and the mark. The metal layer functions to protect the semiconductor device from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes. The present invention also pertains a method of manufacturing the semiconductor device as described. The method involves forming a mark on a semiconductor substrate surface of the device and covering the semiconductor substrate surface and the mark with a layer of metal so that the device is protected from exposure to electromagnetic radiation and allows the mark to be visible for identification purposes.Type: GrantFiled: August 28, 2000Date of Patent: September 10, 2002Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Nikhil Vishwanath Kelkar, Ken Pham
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Patent number: 6398034Abstract: The present invention provides a low cost carrier tape designed to store chips during transportation. The invention comprises a carrier tape which contains receptacle holes designed to secure chips onto the carrier tape by clasping onto the chip's electrical contacts. The receptacle holes prevent the chip from rotating and physically moving. The receptacle holes are formed in patterns to match the standardized electrical contact patterns of flip chip families. The diameters of the receptacle holes may be sized slightly smaller than the diameter of electrical contacts such that a chip is secured by “snap-fitting” each electrical contact into a receptacle hole. Relief slits may be formed on the edges of the receptacle holes to facilitate the “snap-fitting” of electrical contacts into receptacle holes.Type: GrantFiled: February 29, 2000Date of Patent: June 4, 2002Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Nikhil Vishwanath Kelkar
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Patent number: 6384890Abstract: A connection assembly (40) for operably coupling a plurality of independent imaging devices (41, 41′, 41″) to an optical subsystem (42). The connection assembly (40) includes a unitary flex circuit device (43) having an elongated arm portion (45), and a plurality independent finger portions (46, 46′, 46″) extending from a distal end of the arm portion (45). Each finger portion (46, 46′, 46″) defines a coupling region (47, 47′, 47″) adapted to operably couple a respective imaging device (41, 41′, 41″) to a respective finger portion (46, 46′, 46″) for support thereof. The finger portions (46, 46′, 46″) are further adapted to strategically couple each respective imaging device (41, 41′, 41″) to the optical subsystem (42) as a unit. The flex circuit device (30) includes a plurality of circuits (65) terminating at respective terminals (40) of a coupling region (47) thereof.Type: GrantFiled: November 15, 1999Date of Patent: May 7, 2002Assignee: National Semiconductor CorporationInventors: Hem P. Takiar, Ranjan J. Mathew
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Patent number: 6362530Abstract: A method of forming an integrated circuit package includes providing a flip chip integrating circuit die having a first plurality of contacts for electrically connecting the die to other elements. A second plurality of contacts for electrically connecting the integrated circuit package to external elements is also provided. A substrate for supporting the flip chip die and the second plurality of contacts is initially prepared. The substrate includes a connecting arrangement for electrically connecting the first plurality of contacts on the die to the second plurality of contacts. The method includes the step positioning the flip chip integrated circuit die and the second plurality of contacts on the substrate.Type: GrantFiled: April 6, 1998Date of Patent: March 26, 2002Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar
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Patent number: 6352881Abstract: A method and apparatus for forming a layer of underfill adhesive on an integrated circuit located on a wafer surface are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. A layer of underfill adhesive is then formed on the wafer surface such that at least some portion of most of the solder balls remain uncovered. The layer of underfill adhesive is partially cured and the flip chip is then mounted onto a substrate. A solder reflow operation electrically couples the flip chip and the substrate as well as fully cures the underfill adhesive.Type: GrantFiled: July 22, 1999Date of Patent: March 5, 2002Assignee: National Semiconductor CorporationInventors: Luu Nguyen, Nikhil Kelkar, Christopher Quentin, Ashok Prabhu, Hem P. Takiar
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Patent number: 6284566Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.Type: GrantFiled: August 31, 1999Date of Patent: September 4, 2001Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew
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Publication number: 20010015477Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: ApplicationFiled: April 26, 2001Publication date: August 23, 2001Inventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6255141Abstract: Improved methods of packaging external fuses together with integrated circuit devices are described. A pair of frame strips are provided that each have an associated set of contact pads. A resistor paste is applied to one of the contact pad sets and the frame strips are laminated together by curing the resistor paste which is positioned between the contact pad sets. Dice are mounted to the opposite sides of the second contact pads to form integrated circuit devices having integrally packaged external fuses. The packaged devices are eventually singulated for use. In some embodiments, the contact pads each have downturned tabs that form wings on opposite sides of each die. When the dice are flip chips, a device may be attached to a substrate board by soldering both the bumps on the die and the tab wing tips to the substrate board. In a preferred embodiment, the resistor paste is a positive temperature coefficient resistor paste.Type: GrantFiled: September 7, 1999Date of Patent: July 3, 2001Assignee: National Semiconductor CorporationInventors: Inderjit Singh, Hem P. Takiar, Ranjan J. Mathew, Nikhil V. Kelkar
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Patent number: 6245595Abstract: A method and apparatus for forming a layer of underfill encapsulant on an integrated circuit located on a wafer are described. As a flip chip, the integrated circuit has electrically conductive pads, most of which have a solder ball attached thereto. Most of the solder balls have been flattened in order to provide an enlarged solder wetting area. A layer of underfill encapsulant is injected onto the integrated circuit under pressure to form a layer of underfill encapsulant that is then pre-cured. The integrated circuit is mounted to a substrate and the substrate and the integrated circuit are electrically coupled by a solder reflow operation which also finally cures the underfill encapsulant.Type: GrantFiled: July 22, 1999Date of Patent: June 12, 2001Assignee: National Semiconductor CorporationInventors: Luu Nguyen, Hem P. Takiar, Ethan Warner, Shahram Mostafazadeh, Joseph O. Smith
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Patent number: 6238949Abstract: A method and an apparatus for forming a plastic chip on chip module is disclosed. The plastic chip on chip module is formed by placing a stacked chip set into a molding chamber suitably arranged to receive encapsulant. The stacked chip set includes a daughter chip that is electrically and mechanically coupled to a mother chip where the daughter chip is directly aligned to and separated from the mother chip by a standoff gap. Encapsulant is then passed into the molding chamber filling the standoff gap substantially simultaneously with surrounding the chip set to form the plastic chip on chip module.Type: GrantFiled: June 18, 1999Date of Patent: May 29, 2001Assignee: National Semiconductor CorporationInventors: Luu Nguyen, Ashok Prabhu, Nikhil Kelkar, Hem P. Takiar
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Patent number: 6177288Abstract: A method of producing and electrically testing a chip scale integrated circuit package includes the step of providing a panel having a plurality of chip scale packages assembled on the panel. Each of the chip scale packages are electrically isolated from one another by cutting any electrically conductive paths which electrically interconnect the chip scale packages to one another on the panel. The step of electrically isolating the chip scale packages is done without singulating the chip scale packages. The chip scale packages are then individually electrically tested while they remain physically connected to one another on the panel. After the chip scale packages are individually tested, the chip scale packages are singulated.Type: GrantFiled: May 11, 1999Date of Patent: January 23, 2001Assignee: National Semiconductor CorporationInventor: Hem P. Takiar
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Patent number: 6173490Abstract: A method and an apparatus for forming a panel of packaged integrated circuits is disclosed. A substrate panel having an array of integrated circuits mounted thereon is placed in a mold having a molding chamber. The molding chamber has a multiplicity of adjacent package recesses flowably interconnected by way of a plurality of molding compound flowgates. Each package recess is suitable for receiving at least one associated integrated circuits. A molding compound is passed into the molding chamber by way of a mold gate such that at least some of the molding compound passes through a plurality of different package recesses by way of their associated flowgates. In one embodiment, the mold includes a mold body having a molding chamber with a plurality of ridges that define the multiplicity of package recesses within the molding chamber. The multiplicity of package recesses are flowably interconnected through flowgates formed by the ridges.Type: GrantFiled: August 20, 1997Date of Patent: January 16, 2001Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Fred Drummond
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Patent number: 6140708Abstract: An assembly process provides a chip scale package (CSP) which characteristically includes (i) a perforated substrate in which vias can be embedded, (ii) a solder mask on which the integrated circuit die can be attached, and (iii) efficient use of the surface area for electrically routing signals from the integrated circuit die to the external terminals attached to the perforated substrate. The resulting package is highly compact and therefore has a foot print minimally larger than the surface area of the integrated circuit chip. Consequently, the costs of substrate and capsulation materials are minimized. The assembly process allows very high volume production because a large number of integrated circuits can be made on a single unit of the substrate, and singulation is performed in the assembly process at a stage much later than the corresponding stage in a conventional process.Type: GrantFiled: July 8, 1997Date of Patent: October 31, 2000Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew
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Patent number: 6122033Abstract: The present inventions provide a fusible seal for sealing liquid crystal display (LCD) devices. A fusible seal is formed on a transparent plate or on a die having a pixel array. The fusible seal is configured to encircle the pixel array of the die when the die and the transparent plate are joined. The die and the transparent plate are joined together such that the fusible seal is disposed between the transparent plate and the die. Heat is locally applied to the fusible seal without significantly heating the transparent plate or the die. Heating the fusible seal fuses the transparent plate to the die and encloses the pixel array. A LCD device is thereby formed without the need to cure the entire LCD device, which often times causes warping of the LCD device.Type: GrantFiled: April 6, 1998Date of Patent: September 19, 2000Assignee: National Semiconductor CorporationInventors: Ranjan J. Mathew, Hem P. Takiar
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Patent number: 6054338Abstract: A panel of, for example, bismaleimide triazine (BT) or ceramic (Al.sub.2 O.sub.3) is chosen in size to be substantially filled with and taken up by end-result ball grid array (BGA) devices. The end-result devices are positioned closely together and take up substantially the entire area of the initial panel. Structural weakening is provided at appropriate places in the panel to allow the devices to be readily singulated.Type: GrantFiled: February 20, 1998Date of Patent: April 25, 2000Assignee: National Semiconductor CorporationInventors: Shaw Wei Lee, Hem P. Takiar, Ranjan J. Mathew, Hee Jhin Kim
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Patent number: 6024275Abstract: A method of producing an array of interconnecting contacts for an integrated circuit package, such as a flip chip integrated circuit, and connecting the array of interconnecting contacts to the package utilizes a mold to form the array and attach the array to the package. The method may also be used to interconnect two integrated circuit die. The mold defines a desired shape and relative position for a plurality of interconnecting contacts which make up the array of interconnecting contacts. The array of interconnecting contacts are molded by filling the mold with a desired contact forming material such as solder paste. The mold containing the molded array of interconnecting contacts is positioned adjacent to the integrated circuit package such that each interconnecting contact is positioned adjacent to a corresponding contact pad of the integrated circuit package. And finally, the molded interconnecting contacts are attached to their corresponding contact pads of the integrated circuit package.Type: GrantFiled: June 16, 1998Date of Patent: February 15, 2000Assignee: National Semiconductor CorporationInventor: Hem P. Takiar