Abstract: A digital modulator in a radio transmitter includes circuitry for switching between Gaussian Minimum Shift Keying (GMSK) and Phase-Shift Keying (PSK) while maintaining spectral mask requirements. The digital modulator of the present invention includes both GMSK and PSK symbol mappers that produce PSK in-phase and quadrature symbols and GMSK symbols, respectively, to a pulse shaping block. Based on opposite phases of a modulation control signal, the symbol mappers produce either modulated data or a steam of logic zeros to the pulse shaping block. The pulse shaping block filters the received data and multiplexes the data so that each modulated data stream receives non-zero data during a guard time to avoid abrupt changes in the modulated signal that would violate the spectral mask requirements.

Abstract: In an envelope comparison embodiment, a delay calibrator produces a delay signal based on a comparison of a feedback signal and an envelope component of the transmitted signal. A down-converter produces the feedback signal from an outgoing modulated RF signal based on at least one local oscillation. Envelope detectors in the delay calibrator and the envelope signal path are operably coupled to a summing node that produces a delay error signal based on a temporal difference between the two envelopes. One embodiment includes phase detectors to detect and adjust the zero crossings of the feedback signal and the envelope signal path. As the delay mismatch between the envelope signal path and the phase signal path increases, the power spectrum increases in adjacent communication channels. A mask margin measurement technique measures the power level in an adjacent channel and adjusts the envelope path delay accordingly.

Abstract: A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

Abstract: An FSK modulator and applications thereof are disclosed. The FSK modulator comprises a phase-locked loop, a frequency divider module, an image rejection mixer and a summing module. The phase-locked loop is operably coupled to generate a first oscillation from a reference oscillation. The frequency divider module is operably coupled to divide the first oscillation to produce a second oscillation. The image-rejection mixer is operably coupled to mix the second oscillation with a low intermediate oscillation to produce a mixed data signal, and the summing module is operably coupled to sum the mixed data signal with the first oscillation to produce an FSK modulated signal.

Abstract: A radio frequency (RF) transmitter includes a digital radio processor and a baseband processor. A complex analog-to-digital converter (ADC) within the radio processor provides an analog interface to the baseband processor to receive an analog complex modulated baseband signal and convert the analog complex modulated baseband signal to a digital complex modulated baseband signal. A demodulator within the radio processor demodulates the digital complex modulated baseband signal to recreate the original transmit digital data as a demodulated digital signal. The demodulated digital signal is processed by a digital processor in the radio processor to mitigate the effects of various imperfections in the radio processor circuitry.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. Generally, the system is operable to produce digital data based on the filtered IF signals based on an analog feedback signal and upon an offset compensation signal wherein the analog feedback signal is based upon the digital data. Offset compensation logic is operable to detect an amount of DC offset in a digital IF demodulated digital serial data and producing the offset compensation control signal based upon the detected amount of DC. A programmable bias current is operable to substantially cancel a bias voltage component of the received analog feedback signal based upon an offset compensation control signal.

Abstract: A complex digital phase locked loop for use in a digital demodulator includes a phase detector for producing a phase error indicative of a difference in phase between a complex digital input signal and a complex digital feedback signal. The phase error is input to a controller, which multiplies the phase error by a gain factor selected to stabilize and optimize the phase locked loop and produces an output signal for use in extracting a frequency deviation present in the complex digital input signal. The output signal is also input to a numerically controlled oscillator that tracks the phase of the complex digital input signal based on the output signal and produces the complex digital feedback signal.

Abstract: Methods and systems for processing a plurality of signals are disclosed herein. Aspects of the method may comprise amplifying an input signal. The amplified input signal may be bandpass filtered. Amplification of the input signal may be adjusted based on only narrowband received signal strength indication of the bandpass filtered amplified input signal. The amplified input signal may be downconverted and a blocker signal may be bandpass filtered from the amplified input signal. Signal strength of a desired signal from the amplified input signal may be measured. The amplification of the input signal may be adjusted utilizing a triple well (TW) NMOS transistor. A control signal may be generated based on the narrowband received signal strength indication of the bandpass filtered amplified input signal. The amplification of the input signal may be adjusted based on at least one of the generated control signals.

Abstract: A method for processing a plurality of signals may include amplifying an input signal and generating a wideband signal from the amplified input signal. The method may further include bandpass filtering the generated wideband signal to generate a narrowband signal, and adjusting amplification of the input signal based on a narrowband received signal strength indication of the generated narrowband signal, and/or a wideband received signal strength indication of the generated wideband signal. The amplified input signal may be downconverted to generate the wideband signal. The amplified input signal may be downconverted to an intermediate frequency (IF) and/or to a baseband signal to generate the wideband signal. At least one blocker signal may be bandpass filtered from the amplified input signal.

Abstract: A method for calibrating a radio frequency (RF) transmitter begins by mixing a modulated RF signal with an in-phase (I) component of a local oscillation or a quadrature (Q) component of the local oscillation to produce a baseband representation of the modulated RF signal. The method continues by converting the baseband representation of the modulated RF signal into a digital baseband signal. The method continues by filtering the digital baseband signal to produce at least one frequency spectrum component. The method continues by interpreting the at least one frequency spectrum component to produce a calibration signal. The method continues by calibrating at least one of DC offset and gain offset of digital transmitter processing module based on the calibration signal.

Abstract: A loop filter for use in a frequency synthesizer provides improved spurious performance using switched capacitors. The loop filter includes a first switched capacitor having a first capacitance value and which is operable to charge to a first voltage corresponding to a current pulse indicative of a difference in phase or frequency between a reference signal and a feedback signal. The loop filter further includes a second switched capacitor having a second capacitance value and which is operable to charge to a second voltage from the first voltage and produce a control voltage based upon the second voltage. The loop filter has a bandwidth determined by a ratio of the second capacitance value to the first capacitance value.

Abstract: A channel select filter having channel equalization includes a first low pass filter stage, a gain stage, a subtraction module, and a second low pass filter stage. The first low pass filter stage is operably coupled to filter input signals to produce first low pass filtered signals. The gain stage is operably coupled to adjust gain of the input signals to produce gained input signals. The subtraction module is operably coupled to subtract the first low pass filtered signals from the gain input signals to produce first stage signals. The second low pass filter stage is operably coupled to filter the first stage signals to produce channel selected signals.

Abstract: A method for designing an interpolation filter begins by partitioning interpolation filtering into a plurality of interpolation filtering stages that are cascaded together. Each of the plurality of interpolation filtering stages includes an up sampling stage and a filtering stage. The method continues by manipulating a first one of the interpolation filtering stages based on a first digital signal processing identity to produce a first equivalent interpolation filtering stage. The method continues by manipulating a second one of the interpolation filtering stages based on the first digital signal processing identity to produce a second equivalent interpolation filtering stage. The method continues by simplifying the first and second equivalent interpolation filtering stages to produce at least a simplified portion of the interpolation filter.

Abstract: The present invention implements an architecture that changes the sequence of digital processing so that equalization occurs prior to phase accumulation. A phase differentiator receives an envelope path phase signal to produce a differentiated phase signal to an equalizer. The transfer function of the phase differentiator is implemented so that it cancels, except for a one-cycle delay, the transfer function of the phase accumulator. This cancellation substantially eliminates accumulation of the envelop path phase signal. Additionally, a dither signal added to the quantization nodes in the equalizers shifts the spectral content of the quantization noise such that the phase accumulator sees the quantization noise as zero mean white noise. Implemented as one of a rounding or flooring quantizer, biquad filters in the equalizers round or truncate the equalizer output to a minimal bit width based on a desired output phase error.

Abstract: An integrated circuit radio frequency (RF) transmitter includes a phase locked loop having a multi-mode loop filter that is operable to provide wide band response with a fast settle time in a startup mode of operation and a relatively more narrow response with a longer settle time but with improved filtering in a steady state mode of operation according to one embodiment of the invention. The multi-mode loop filter includes, in one embodiment, selectable resistance circuitry for selecting between a plurality of resistance values based upon a two-state multi-mode control signal to provide the selected resistance values and selectable capacitance circuitry for selecting between a plurality of capacitance values based upon the two-state multi-mode control signal and for operatively coupling selected capacitors to selected resistors to provide the selected capacitance values.

Abstract: The present invention provides a radio transmitter having a digital modulator that further includes logic for continuous amplitude and continuous phase modulation switching in an RF transmitter intended to support both frequency shift keying (FSK) and phase shift keying (PSK) modulation techniques in a smooth and continuous manner that does not violate spectral mask requirements. The invention supports continuous modulation switching both ways, i.e., from FSK to PSK and from PSK to FSK. In operation, the radio transmitter initially operates in a first communication mode, transmitting communication signals to a remote agent according to a first modulation technique at a first data rate and then transitions to the second modulation type at a second data rate without spectral mask violation.

Abstract: A radio transmitter within a transceiver includes a digital processor and analog circuitry for modulating and transmitting an outgoing digital signal in multiple modes of operation. The digital processor digitally modulates the outgoing digital signal to produce one of a constant envelope modulated digital signal and a variable envelope modulated digital signal based on the particular modulation scheme being used to modulate the outgoing digital signal. In addition, the digital processor filters the outgoing digital signal using filter values selected based on the signal bandwidth of the outgoing digital signal. The analog circuitry converts digital envelope and phase signals of the modulated digital signal to analog envelope and phase signals, and up-converts the analog phase signal from an IF signal to an RF signal, using a loop filter that is programmable based on the signal bandwidth of the outgoing digital signal.

Abstract: A radio receiver includes a low noise amplifier, a down conversion module, an analog to digital converter, and a digital demodulator. The digital demodulator is operably coupled to convert the digital low IF signals into inbound digital symbols and includes a baseband conversion module, a filtering module, a programmable equalizer, a CORDIC module, and a demodulation module. The programmable equalizer is operably coupled to equalize phase and frequency response of filtered digital baseband signals from the filtering module such that the phase and frequency response of the filtered digital baseband signals approximates phase and frequency response of a square root raised cosine filter to produce adjusted digital baseband signals. The CORDIC module is operably coupled to produce phase and magnitude information from the adjusted digital baseband signals. The demodulation module is operably coupled to produce the inbound digital symbols from the phase and magnitude information.

Abstract: A polar transmitter includes a digital processor coupled to receive a complex modulated digital signal and a feedback signal produced from the complex modulated digital signal and that is operable to compare the complex modulated digital signal to the feedback signal to determine an error signal indicative of a difference between the complex modulated digital signal and the feedback signal. The digital processor is further operable to produce a correction signal from the error signal and to add the correction signal to the complex modulated digital signal to produce a corrected complex modulated digital signal.

Abstract: A polar transmitter includes a digital processor for producing a phase correction signal and a complex modulated digital signal including a digital phase-modulated signal. The phase correction signal is added to the digital phase-modulated signal to produce a corrected digital phase signal. The corrected digital phase signal is input to a phase-locked loop (PLL) to produce an RF phase signal that tracks the phase of the digital phase-modulated signal based on the corrected digital phase signal.