Abstract: Digital signal processing generates IF modulated digital data which is then converted to analog using a high sample rate digital-to-analog converter (DAC) without first producing a baseband signal that is to be upconverted to IF. The digital data has a high sample rate that is a whole multiple of a specified IF signal. A DAC converts the digital data into a continuous waveform IF signal that is produced to a feed-forward filter that eliminates spectral copies of the signal. The sample rate is selected so that harmonic signals do not appear in specified signal bands. Various embodiments include sample rates of 104 and 338 MHz (GSM application). The 26 MHz IF filtered signal produced by the feed-forward filter is then produced to a translational loop that produces a corresponding output oscillation (RF transmit signal).

Abstract: An RF transmitter includes a digital processor that includes a time shift signal determination block that produces a time shift signal based upon a bleed over power level in an adjacent channel resulting from downstream phase and magnitude mismatch of a primary signal. In one embodiment, the time shift signal determination block includes logic and circuitry for determining a power ratio for a primary signal between a bleed over power level in an adjacent channel and the primary channel. The time shift signal determination block produces the time shift signal to a time shift block that is operably coupled to receive one of an envelope magnitude component and a phase component from a digital signal generation block, wherein the time shift block generates a time shift in at least one of the envelope signal path and the phase signal path based upon the time shift signal.

Abstract: Radio transceiver circuitry includes I/Q imbalance compensation logic within at least one of a digital modulator or a digital demodulator, depending upon whether the I/Q imbalance compensation block is compensating for I/Q imbalance in a transmit path or in a receive path. For a transmitter, a digital processor includes a baseband processor that produces transmit data (digital data) for transmission to a digital modulator that includes an I/Q imbalance compensation logic. The digital modulator, which may modulate in any known modulation scheme, produces in-phase and quadrature phase components that have been pre-compensated for I/Q imbalance that is introduced by downstream analog circuitry in the transmit path. In at least one embodiment of the invention, a “steepest descent” algorithm for finding optimal values of I/Q imbalance compensation parameters based upon a small number of image rejection measurements are used.

Abstract: A frequency synthesizer for use in a transceiver generates a relatively high reference frequency with fine frequency resolution and low in-band phase noise by using a digital processor to generate a digital reference signal at a finely-tuned reference frequency. A Digital-to-Analog Converter (DAC) converts the digital reference signal to an analog reference signal, and a low pass filter filters the analog reference signal to produce a filtered analog reference signal. The frequency synthesizer further includes a phase locked loop for up-converting the filtered analog reference signal from an IF signal to an RF signal.

Abstract: A polar transmitter includes a two-point modulation phase-locked loop (PLL) for producing an RF signal with a wide bandwidth. The PLL includes a first input for receiving a phase signal of a variable-envelope modulated signal and providing the phase signal along a first signal path to produce a first frequency modulation signal and a second input for receiving the phase signal and providing the phase signal along a second signal path to produce a second frequency modulation signal. The PLL further includes a voltage controlled oscillator (VCO) having two modulation points, one for receiving the first frequency modulation signal and the other for receiving the second frequency modulation signal. The VCO is controlled by an aggregate of the first frequency modulation signal and the second frequency modulation signal to up-convert the phase signal from an IF to an RF to produce the RF signal with a wide bandwidth.

Abstract: A radio receiver includes a low noise amplifier, intermediate frequency mixing stage, complex bandpass filter, a single analog to digital converter, a 1st digital mixing module, and a 2nd digital mixing module. The low noise amplifier is operably coupled to amplify a modulated radio frequency (RF) signal to produce an amplified modulated RF signal. The intermediate frequency mixing stage is operably coupled to mix the amplified modulated RF signal with a local oscillation to produce a modulated IF signal. The complex bandpass filter filters an I and Q component of the modulated IF signal to produce a filtered IF signal. The single analog to digital converter is operably coupled to convert the filtered IF signal into a digital IF signal. The 1st and 2nd mixing modules each receive the digital IF signal and mix the digital IF signal with an in-phase and quadrature digital local oscillation to produce a 1st baseband signal component and a 2nd baseband signal component.

Abstract: A Continuous-Time Delta-Sigma Analog-to-Digital Converter (CT??ADC) for a radio frequency (RF) receiver employing a 200 kHz IF realizes an optimal signal-to-noise ratio using a programmable resonator that is set to resonate at 200 kHz. The programmable resonator is operably coupled to receive both an analog input signal at a low IF of 200 kHz and an analog feedback signal. From the analog input signal and the analog feedback signal, the programmable resonator produces a resonate signal at the low IF, and provides the resonate signal to a quantizer. The quantizer produces a digital output having a digital value coarsely reflecting an amplitude of the analog input signal. The CT??ADC further includes at least one programmable digital-to-analog converter (DAC) operably coupled to receive the digital output and to convert the digital output into the analog feedback signal provided to the programmable resonator.

Abstract: Digital calculation of an RSSI value begins by digitally calculating a magnitude of a signal (e.g., a received RF signal or representation thereof). The process then continues by filtering the magnitude of the signal to produce a filtered magnitude signal. The process then continues by determining a coarse RSSI value of the filtered magnitude signal, wherein the coarse RSSI value indicates a sliding window of RSSI values. Once the coarse RSSI value is obtained, the process continues by determining a fine RSSI value within the sliding window of RSSI values. The process concludes by summing the fine RSSI value with the coarse RSSI value to produce a digital RSSI value.

Abstract: The present invention employs a mixture of digital signal processing and analog circuitry to reduce spurious noise in continuous time delta sigma analog-to-digital converters (CT??ADCs). Specifically, a small amount of random additive noise, also referred to as dither, is introduced into the CT??ADC to improve linear behavior by randomizing and de-correlating the quantization noise from the input signal without significantly degrading the SNR performance. In each of the embodiments, digital circuitry is used to generate the desired randomness, de-correlation, and spectral shape of the dither and simple analog circuit blocks are used to appropriately scale and inject the dither into the CT??ADC loop. In one embodiment of the invention, random noise is added to the quantizer input.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: A direct conversion or VLIF receiver corrects DC offset by, prior to receiving a burst of data, the receiver determines a coarse DC offset with the antenna of the receiver switched off. The receiver then adjusts an analog portion of the receiver (e.g., the output of the mixers) based on the coarse DC offset. The receiver then determines a gain setting of the receiver (e.g., for the low noise amplifier and/or programmable gain amplifiers) with the antenna on. The receiver then sets the gain of at least one gain stage of the receiver based on the gain setting. The receiver then determines a fine DC offset with the antenna off. The receiver then, while receiving a burst of data, subtracts the fine DC offset from the digital baseband or low IF signal prior to data recovery.

Abstract: A method and apparatus for trimming of a local oscillation within a radio frequency integrated circuit (RFIC) includes processing that begins when an RFIC receives a radio frequency (RF) signal having a known frequency. The processing then continues when the RFIC mixes the RF signal with a receiver local oscillation to produce a low intermediate frequency (IF) signal, which may have a carrier frequency of zero (i.e., a baseband signal) or up to a few mega Hertz). The processing then continues when the RFIC demodulates the low IF signal to produce demodulated data. The processing then continues as the RFIC determines a DC offset from the demodulated data, where the DC offset is reflective of the difference between the known frequency and the frequency of the receiver local oscillation. The processing then continues as the RFIC adjusts the receiver local oscillation to reduce the DC offset when the DC offset compares unfavorably with an allowable offset threshold.

Abstract: A self-calibrating transmitter includes an up-conversion mixing module, summing module, calibration determination module, and a calibration execution module. The up-conversion mixing module is operably coupled to mix an I component of a base-band signal with an I component of a local oscillation to produce a mixed I signal and is also operably coupled to mix a Q component of the base-band signal with a Q component of the local oscillation to produce a mixed Q signal. The summing module sums the mixed I signal with the mixed Q signal to produce a modulated radio frequency (RF) signal. The calibration determination module is operably coupled to produce a calibration signal, which it generates by interpreting the local oscillation and the modulated RF signal. The calibration execution module is operably coupled to calibrate the DC level of the I and/or Q component of the base-band signal, and/or the gain of the I and/or Q component of the base-band signal based on the calibration signal.

Abstract: The present invention provides an efficient method for near-unity sampling rate alteration in high performance applications, such as CD to DAT conversion. Specifically, the input digital signal is first interpolated by a factor of eight and lowpass filtered to form an intermediate signal. A clamped cubic spline interpolator (CCSI) algorithm is then employed to accurately interpolate the intermediate signal to points in-between adjacent samples of the intermediate signal as required by the 48 kHz output sampling rate. The CCSI is highly accurate due to highly accurate derivative estimates arrived at by repeated Richardson extrapolation. In the example CD to DAT converter covered in detail, fourth order Richardson extrapolation is employed. It is shown by this example that the proposed method yields the desired performance, is computationally efficient and requires little storage.

Abstract: An FM radio receiver includes a low noise amplifier, down conversion mixing module, local oscillation module, bandpass filter, demodulation module, and a DC offset estimation module. The low noise amplifier, the down conversion mixing module, the bandpass filter, and the demodulation module are operably coupled to recapture data from a received a radio frequency (RF) signal. The local oscillation module is operably coupled to generate the local oscillation based on a reference oscillation and a DC offset correction signal. The DC offset estimation module is operably coupled to generate the DC offset correction signal based on a determined a DC offset. The DC offset estimation module determines the DC offset prior to compensation of the local oscillation, such as during a test sequence and/or during a preamble.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A transmit signal generated by the baseband processor in a translational loop type RF transmitter is “pre-distorted” so as to counter act magnitude distortion and group delay variation imposed by a narrow PLL signal filter. The pre-distortion occurs in two steps: a magnitude equalizer in the baseband processor pre-distorts the amplitude of the transmit signal according to the inverse of the PLL signal filter magnitude response, and a group delay equalizer linearizes the phase response of the entire transmitter chain, i.e., pre-distorts the transmit signal such that the combined phase response of magnitude equalizer, group delay equalizer, and PLL signal filter is linear. With such pre-distortion, a loop filter is provided for with component values that define a relatively small bandwidth for the loop filter to filter spurious tones that result from an IF reference feedthrough to a voltage controlled oscillator of the translational loop.

Abstract: A method for calibrating a phase locked loop begins by determining a gain offset of a voltage controlled oscillator of the phase locked loop. The processing then continues by adjusting current of a charge pump of the phase locked loop based on the gain offset.

Abstract: A scaled input current is produced that substantially matches the full scale input of a CT??ADC that substantially cancels an offset bias current component of the input current. A variable bias resistance value is coupled between the integrator input and one of a supply voltage and a circuit common. The method further includes integrating the input current to produce an integrated signal representing a time averaged value of the input current to substantially remove noise from a frequency band of interest. The integrated signal is produced to a quantizer to produce a feedback current that substantially cancels a quantization noise component in the digital representation of the scaled analog signal by coupling the digital representation of the scaled analog signal to a programmable digital switch wherein the programmable digital switch either sinks current from or sources current to the integrator input.

Abstract: A differential linear fractional N-synthesizer includes a phase and frequency detection module, a linearized charge pump, a low pass filter, a voltage controlled oscillator, and a fractional N divider feedback. The phase and frequency detection module is operably coupled to produce a differential charge-up signal, a differential charge-down signal, or a differential off signal based on phase and/or frequency differences between a reference oscillation and a feedback oscillation. The feedback oscillation is generated by the fractional N divider feedback, which divides an output oscillation by a divider value to produce the feedback oscillation. The linearized charge pump includes a 1st current source, a 2nd current source and a modulation module. In response to the differential off signal, the modulation module produces a modulated differential off signal that causes the 1st and 2nd current sources to produce a zero current signal in an alternating fashion.