Patents by Inventor Henry P. Moreton
Henry P. Moreton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9652815Abstract: A graphics processing subsystem and a method of shading are provided. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to create the particular composite texel.Type: GrantFiled: September 11, 2012Date of Patent: May 16, 2017Assignee: Nvidia CorporationInventors: Cass W. Everitt, Henry P. Moreton
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Patent number: 9013498Abstract: A system and method for tracking and reporting texture map levels of detail that are computed during graphics processing allows for efficient management of texture map storage. Minimum and/or maximum pre-clamped texture map levels of detail values are tracked by a graphics processor and an array stored in memory is updated to report the minimum and/or maximum values for use by an application program. The minimum and/or maximum values may be used to determine the active set of texture map levels of detail that is loaded into graphics memory.Type: GrantFiled: December 19, 2008Date of Patent: April 21, 2015Assignee: NVIDIA CorporationInventors: John S. Montrym, Andrew J. Tao, Henry P. Moreton, Emmett M. Kilgariff, Cass W. Everitt, Alexander L. Minkin, Eric Anderson, Yan Yan Tang, Jerome F. Duluk, Jr.
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Patent number: 8941669Abstract: Frames are rendered by multiple graphics processors (GPUs), which may be heterogeneous. Graphics processors split the execution of the command in a push buffer of a frame. One GPU begins rendering a frame, and a second GPU takes over rendering that frame after the second GPU is done rendering a previous frame. The second GPU may then begin rendering a subsequent frame.Type: GrantFiled: July 30, 2007Date of Patent: January 27, 2015Assignee: NVIDIA CorporationInventor: Henry P. Moreton
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Patent number: 8730252Abstract: A system, method and computer program product are provided for bump mapping in a hardware graphics processor. Initially, a first set of texture coordinates is received. The texture coordinates are then multiplied by a matrix to generate results. A second set of texture coordinates is then offset utilizing the results. The offset second set of texture coordinates is then mapped to color.Type: GrantFiled: March 31, 2004Date of Patent: May 20, 2014Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Publication number: 20140071128Abstract: A graphics processing subsystem and a method of shading. In one embodiment, the subsystem includes: (1) a memory configured to contain a texel data structure according to which multiple primitive texels corresponding to a particular composite texel are contained in a single page of the memory and (2) a graphics processing unit configured to communicate with the memory via a data bus and execute a shader to fetch the multiple primitive texels contained in the single page to create the particular composite texel.Type: ApplicationFiled: September 11, 2012Publication date: March 13, 2014Applicant: Nvidia CorporationInventors: Cass W. Everitt, Henry P. Moreton
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Patent number: 8493395Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.Type: GrantFiled: July 16, 2012Date of Patent: July 23, 2013Assignee: Nvidia CorporationInventors: Jerome F. Duluk, Jr., Henry P. Moreton, Steven E. Molnar, John S. Montrym
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Patent number: 8321849Abstract: A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.Type: GrantFiled: January 26, 2007Date of Patent: November 27, 2012Assignee: NVIDIA CorporationInventors: John R. Nickolls, Henry P. Moreton, Lars S. Nyland, Ian A. Buck, Richard C. Johnson, Robert S. Glanville, Jayant B. Kolhe
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Publication number: 20120284568Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.Type: ApplicationFiled: July 16, 2012Publication date: November 8, 2012Applicant: NVIDIA CorporationInventors: Jerome F. Duluk, JR., Henry P. Moreton, Steven E. Molnar, John S. Montrym
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Patent number: 8264492Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.Type: GrantFiled: November 19, 2007Date of Patent: September 11, 2012Assignee: NVIDIA CorporationInventors: John Erik Lindholm, David B. Kirk, Henry P. Moreton, Simon Moy
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Patent number: 8259122Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.Type: GrantFiled: November 19, 2007Date of Patent: September 4, 2012Assignee: NVIDIA CorporationInventors: John Erik Lindholm, David B. Kirk, Henry P. Moreton, Simon Moy
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Patent number: 8228338Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.Type: GrantFiled: January 19, 2007Date of Patent: July 24, 2012Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., Henry P. Moreton, Steven E. Molnar, John S. Montrym
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Patent number: 8094158Abstract: Systems and methods for using multiple versions of programmable constants within a multi-threaded processor allow a programmable constant to be changed before a program using the constants has completed execution. Processing performance may be improved since programs using different values for a programmable constant may execute simultaneously. The programmable constants are stored in a constant buffer and an entry of a constant buffer table is bound to the constant buffer. When a programmable constant is changed it is copied to an entry in a page pool and address translation for the page pool is updated to correspond to the old version (copy) of the programmable constant. An advantage is that the constant buffer stores the newest version of the programmable constant.Type: GrantFiled: January 31, 2006Date of Patent: January 10, 2012Assignee: NVIDIA CorporationInventors: Roger L. Allen, Cass W. Everitt, Henry P. Moreton, Thomas H. Kong
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Patent number: 8074058Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.Type: GrantFiled: June 8, 2009Date of Patent: December 6, 2011Assignee: MIPS Technologies, Inc.Inventors: Timothy J. Van Hook, Peter Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian
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Publication number: 20110055497Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.Type: ApplicationFiled: September 3, 2010Publication date: March 3, 2011Applicant: MIPS Technologies, Inc.Inventors: Timothy J. VAN HOOK, Peter Yan-Tek Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian
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Patent number: 7889208Abstract: A system, method and computer program product are provided for computer graphics processing. In use, a value is modified based on an algorithm. An operation is subsequently performed on pixel data taking into account the modified value.Type: GrantFiled: March 18, 2004Date of Patent: February 15, 2011Assignee: NVIDIA CorporationInventors: Henry P. Moreton, John Erik Lindholm, Matthew N. Papakipos, Harold Robert Feldman Zatz
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Patent number: 7880747Abstract: A technique for handling floating-point special values, e.g., Infinity, NaN, ?Zero, and denorms, during blend operations is provided so that blend operations on fragment color values that contain special values can be performed in compliance with special value handling rules. In particular, the presence of special values is detected or the potential presence of special values is detected. This information is used to qualify when blend optimizations may be performed, so that floating point blend operations can remain conformant to special value handling rules.Type: GrantFiled: December 13, 2006Date of Patent: February 1, 2011Assignee: NVIDIA CorporationInventors: Steven E. Molnar, Jerome F. Duluk, Jr., Henry P. Moreton, Daniel P. Wilde, Mark J. French, Bengt-Olaf Schneider, Jonathan J. Dunaisky, Weizhong Xu
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Patent number: 7793077Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.Type: GrantFiled: February 6, 2007Date of Patent: September 7, 2010Assignee: MIPS Technologies, Inc.Inventors: Timothy J. Van Hook, Peter Yan-Tek Hsu, William A. Huffman, Henry P. Moreton, Earl A. Killian
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Patent number: 7755636Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.Type: GrantFiled: November 19, 2007Date of Patent: July 13, 2010Assignee: NVIDIA CorporationInventors: John Erik Lindholm, David B. Kirk, Henry P. Moreton, Simon Moy
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Patent number: 7739556Abstract: A method and system for overriding state information programmed into a processor using an application programming interface (API) avoids introducing error conditions in the processor. An override monitor unit within the processor stores the programmed state for any setting that is overridden so that the programmed state can be restored when the error condition no longer exists. The override monitor unit overrides the programmed state by forcing the setting to a legal value that does not cause an error condition. The processor is able to continue operating without notifying a device driver that an error condition has occurred since the error condition is avoided.Type: GrantFiled: November 2, 2007Date of Patent: June 15, 2010Assignee: NVIDIA CorporationInventors: Jerome F. Duluk, Jr., Henry P. Moreton, John S. Montrym, Nathaniel C. Voorhies
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Patent number: 7697008Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.Type: GrantFiled: February 28, 2007Date of Patent: April 13, 2010Assignee: NVIDIA CorporationInventors: John Erik Lindholm, David B. Kirk, Henry P. Moreton, Simon Moy