Abstract: A fixed function engine and method are described for processing a set of primitive commands. One embodiment of the fixed function engine includes a means for receiving one or more primitive commands, where each such primitive command includes information for processing vertex data using a user-developed program or subroutine. The fixed function engine also includes a means for determining a set of related primitive commands from the received primitive commands and a means for identifying a first primitive command to process from that set. In addition, the fixed function engine includes a means for transmitting a first program command, which is related to the first primitive command, to a processing engine for processing.

Abstract: An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

Abstract: The present invention comprises a computer implemented process and system for rendering curves or surfaces as 3D graphics on a display. The system of the present invention includes a computer system having a processor, a bus, and a 3D graphics rendering pipeline. The curves or surfaces are modeled by non-uniform rational B-splines (NURBS). The process of the present invention functions by receiving a NURBS model for rendering from a software program running on the host processor. The NURBS model defines a curve or surface. The process of the present invention efficiently converts the NURBS model to a Bezier model using the hardware of the graphics rendering pipeline. The Bezier model describes the same curve or surface. The process of the present invention subsequently generates a plurality of points on the curve or surface using the Bezier model and the graphics rendering pipeline. The points are then used by the graphics rendering pipeline to render the curve or surface defined by the Bezier model.

Abstract: A programmable geometry engine is described. One embodiment of the programmable geometry engine includes a programmable primitive engine configured to receive primitive commands that include information for processing vertex data using user-developed programs or subroutines. The programmable primitive engine also is configured to transmit program commands that include program pointers and data pointers. In addition, the programmable geometry engine includes a processing engine configured to receive the program commands. The processing engine is further configured to retrieve the user-developed programs or subroutines using the program pointers and to retrieve vertex data using the data pointers. Also, the processing engine is configured to process the vertex data based on instructions included in the user-developed programs or subroutines to produce processed vertex data and to transmit results to the programmable primitive engine.

Abstract: A system, method and computer program product are provided for programmable pixel processing in a computer graphics pipeline. Initially, pixel data is received from a source buffer. Thereafter, programmable operations are performed on the pixel data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register.

Abstract: A system, method and computer program product are provided for computer graphics processing. Initially, a height parameter is determined. Thereafter, a depth-direction component of the height parameter is calculated. A depth-value of a pixel is then modified utilizing the computed depth-direction component of the height parameter.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A system, method and computer program product are provided for improving image quality in a graphics pipeline. Initially, a difference is detected between a first pixel of a first frame to be outputted and a corresponding second pixel of a second frame outputted before the first frame. Such difference may be representative of motion which is capable of reducing image quality. A pixel output is then modified if such a difference is detected. This is accomplished utilizing texturing hardware in the graphics pipeline. Thereafter, the pixel output is outputted via a progressive or interlaced display system.

Abstract: A representation is provided for displacement mapping. Included are a coarse first mesh, and a fine second mesh with a topology substantially similar to a topology of the first mesh. The second mesh includes a plurality of scalar values which each represent an offset between various points on the first mesh and the second mesh.

Abstract: An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

Abstract: A system, method and article of manufacture are provided for computer graphics processing. First, pixel data is received including a depth-value. Thereafter, the depth-value is modified based on a depth-component of an algorithm. An operation is subsequently performed on the pixel data taking into account the modified depth-value.

Abstract: A system and associated method are provided for processing pixel data in a graphics pipeline. Included is a triangle module coupled to a rasterizer for calculating a plurality of equations using pixel data received from the rasterizer. Also provided is a shader core module coupled to the rasterizer for receiving the pixel data therefrom. The shader core module is further coupled to the triangle module for receiving the equations therefrom. The shader core module functions to execute floating point calculations and generating texture coordinates using the pixel data. Coupled to the shader core module is a texture module. The texture module is capable of looking up texture values using the texture coordinates. Associated therewith is a shader back end module coupled to the texture module and the triangle module. The shader back end module is capable of converting the texture values to an appropriate floating point representation and generating color values using the equations.

Abstract: A system, method and article of manufacture are provided for converting triangular patches into a form suitable for being rendered using a graphics pipeline adapted to render quadrilateral patches. First, a triangular patch is received. The received triangular patch is then divided into a plurality of quadrilateral patches. Such quadrilateral patches are suitable for being processed by a graphics pipeline specifically equipped to render quadrilateral patches.

Abstract: A system, method and article of manufacture are provided for decomposing surfaces using guard curves for rendering purposes during computer graphics processing. Initially, a patch is received. Thereafter, a plurality of strip curves associated with the patch is defined in a first predetermined direction. As such, areas are defined by the strip curves which are adapted for being decomposed into a plurality of primitives. Next, at least one guard curve associated with the patch is generated. The guard curve is positioned along ends of the strip curves and in a second predetermined direction perpendicular with respect to the first predetermined direction.

Abstract: A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

Abstract: An integrated graphics pipeline system is provided for graphics processing. Such system includes a tessellation module that is positioned on a single semiconductor platform for receiving data for tessellation purposes. Tessellation refers to the process of decomposing either a complex surface such as a sphere or surface patch into simpler primitives such as triangles or quadrilaterals, or a triangle into multiple smaller triangles. Also included on the single semiconductor platform is a transform module adapted to transform the tessellated data from a first space to a second space. Coupled to the transform module is a lighting module which is positioned on the single semiconductor platform for performing lighting operations on the data received from the transform module. Also included is a rasterizer coupled to the lighting module and positioned on the single semiconductor platform for rendering the data received from the lighting module.

Abstract: A system, method and article of manufacture are provided for decomposing surfaces for rendering purposes during computer graphics processing. Initially, an interior mesh of primitives is defined in a surface to be rendered. Next, a plurality of surrounding meshes is defined along sides of the interior mesh. The exterior sides of the surrounding meshes each include a plurality of equally sized segments and at least one fractional segment that is a fraction of the equally sized segments. With this configuration, a pattern of triangles is used that permits the number of triangles to be varied continuously from frame to frame while accommodating incremental evaluation techniques such as forward differencing without visual artifacts such as popping.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: A method and arrangement for a dma transfer mode having multiple transactions is provided. The invention generates a set of transaction entries for a DMA transfer each of which contains information related to the address and command instruction of a transaction. The transaction entries are stored in an address/cmd-output-FIFO. The invention negotiates for the control of the system bus. Upon gaining control of the bus, the commands and address relate to each transaction are sequentially place on the system bus. If the transaction is a read operation, data received back from the system bus is first stored in a data-in-FIFO before being sent to the desired destination. If the transaction is a write operation, the data to be transferred is first stored in a data-out-FIFO before being timely place on the system bus for transferring to the desired destination. In either case, the number of data words transferred is monitored to determine when a transaction is complete.