Abstract: The present invention comprises a computer implemented process and system for rendering curves or surfaces as 3D graphics on a display. The system of the present invention includes a computer system having a processor, a bus, and a 3D graphics rendering pipeline. The curves or surfaces are modeled by non-uniform rational B-splines (NURBS). The process of the present invention functions by receiving a NURBS model for rendering from a software program running on the host processor. The NURBS model defines a curve or surface. The process of the present invention efficiently converts the NURBS model to a Bezier model using the hardware of the graphics rendering pipeline. The Bezier model describes the same curve or surface. The process of Bezier model and the graphics rendering pipeline. The points are then used by the graphics rendering pipeline to render the curve or surface defined by the Bezier model.

Abstract: Systems and methods for addressing memory using non-power-of-two virtual memory page sizes improve graphics memory bandwidth by distributing graphics data for efficient access during rendering. Various partition strides may be selected for each virtual memory page to modify the number of sequential addresses mapped to each physical memory partition and change the interleaving granularity. The addressing scheme allows for modification of a bank interleave pattern for each virtual memory page to reduce bank conflicts and improve memory bandwidth utilization. The addressing scheme also allows for modification of a partition interleave pattern for each virtual memory page to distribute accesses amongst multiple partitions and improve memory bandwidth utilization.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into first and second vector registers, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, the first vector register and the second vector register are read from the register file. The present invention executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The resulting element of the execution is then written into the accumulator. Then, the resulting element is transformed into an N-bit width element and written into a third register for further operation or storage in memory. The transformation of the resulting element can include, for example, rounding, clamping, and/or shifting the element.

Abstract: Vertices defining a graphics primitive are converted into homogeneous space and clipped against a single clipping plane, the w=0 plane, to produce a clipped graphics primitive having vertices including w coordinates that are greater than or equal to zero. Rasterizing a graphics primitive having a vertex with a w coordinates that is greater than or equal to zero is less complex than rasterizing a graphics primitive having a vertex with a w coordinate that is less than zero. Clipping against the w=0 plane is less complex than conventional clipping since conventional clipping may require that the graphics primitive be clipped against each of the six faces of the viewing frustum to produce a clipped graphics primitive.

Abstract: Vertices defining a graphics primitive may be processed in homogeneous space and projected into normalized device coordinate space by dividing each coordinate of a vertex by w. When the w coordinate for a vertex is equal to zero, the projected coordinates are set equal to the homogeneous coordinate values. During a viewport transform operation, only the viewport scale is applied rather than applying the viewport scale and viewport bias to produce the vertex in device coordinate space (screen space). Furthermore, when an edge slope is computed for a vertex with a w coordinate equal to zero, the slope is set equal to the vertex in device coordinate space rather than the difference of the two vertices defining the edge. Therefore, a vertex at infinity is correctly positioned avoiding the introduction of visual artifacts.

Abstract: A virtual architecture and instruction set support explicit parallel-thread computing. The virtual architecture defines a virtual processor that supports concurrent execution of multiple virtual threads with multiple levels of data sharing and coordination (e.g., synchronization) between different virtual threads, as well as a virtual execution driver that controls the virtual processor. A virtual instruction set architecture for the virtual processor is used to define behavior of a virtual thread and includes instructions related to parallel thread behavior, e.g., data sharing and synchronization. Using the virtual platform, programmers can develop application programs in which virtual threads execute concurrently to process data; virtual translators and drivers adapt the application code to particular hardware on which it is to execute, transparently to the programmer.

Abstract: Method and apparatus for neighbor and edge indexing is described. A vertex is identified and assigned a reference. One-ring neighbor vertices of the vertex are identified. The reference is assigned to each of the one-ring neighbor vertices identified. An index to one of the one-ring neighbor vertices is assigned. The index is successively incremented to provide indices for each of the one-ring neighbor vertices remaining. Edge indexing follows as described above, with the vertex and its one-ring neighbors defining end points of edges. Additionally, offset indexing is described, and may be used for a consistent order of computation.

Abstract: A method for delayed frame buffer merging. The method includes accessing a polygon that relates to a group of pixels stored at a memory location, wherein each of the pixels has an existing color. A determination is made as to which of the pixels are covered by the polygon, wherein each pixel includes a plurality of samples. A coverage mask is generated corresponding the samples that are covered by the polygon. The group of pixels is updated by storing the coverage mask and a color of the polygon in the memory location. At a subsequent time, the group of pixels is merged into a frame buffer.

Abstract: Systems and methods for shaping a shared edge between two or more N-patches may be used to eliminate gaps when normal vectors along a shared edge are not equal. More particularly, vertices and normals of a polygon, tristip, quadstrip and so on, are obtained. Shared vertices corresponding to the shared edge are identified. When normal vectors at a shared vertex are determined to differ, tangents of the normal vectors are computed. These tangents may be used to optionally shape the shared edge, along with control points.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and pixel types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.

Abstract: A system, method and article of manufacture are provided for programmable processing in a computer graphics pipeline. Initially, data is received from a source buffer. Thereafter, programmable operations are performed on the data in order to generate output. The operations are programmable in that a user may utilize instructions from a predetermined instruction set for generating the same. Such output is stored in a register. During operation, the output stored in the register is used in performing the programmable operations on the data.

Abstract: The present invention provides alignment and ordering of vector elements for SIMD processing. In the alignment of vector elements for SIMD processing, one vector is loaded from a memory unit into a first register and another vector is loaded from the memory unit into a second register. The first vector contains a first byte of an aligned vector to be generated. Then, a starting byte specifying the first byte of an aligned vector is determined. Next, a vector is extracted from the first register and the second register beginning from the first bit in the first byte of the first register continuing through the bits in the second register. Finally, the extracted vector is replicated into a third register such that the third register contains a plurality of elements aligned for SIMD processing. In the ordering of vector elements for SIMD processing, a first vector is loaded from a memory unit into a first register and a second vector is loaded from the memory unit into a second register.

Abstract: Method and apparatus for generating a primitive extension defining a generalized primitive is described. The primitive extension defines the connectivity and vertices used to specify a collection of connected primitives, such as a strip-type or fan-type generalized primitive. A generalized primitive includes a number of vertices where some of the vertices are shared with neighboring primitives. The primitive extension includes an originating primitive, vertex data, and connectivity information. The primitive extension provides a general interface for describing a variety of connected primitives.

Abstract: Method and apparatus for providing texture and/or alpha compression. In one embodiment, the present invention incorporates stored palettes, e.g., a luminance palette and a chrominance palette such that, compressed texture data pertaining to a fixed blocksize is decoded and applied to the stored palettes to extract the texel data. In a second embodiment, the present method uses a plane to estimate the alpha value at each of the texels, and a three-bit correction factor to adjust the estimate to produce a final alpha value.

Abstract: The present invention provides extended precision in SIMD arithmetic operations in a processor having a register file and an accumulator. A first set of data elements and a second set of data elements are loaded into a first vector register and a second vector register, respectively. Each data element comprises N bits. Next, an arithmetic instruction is fetched from memory. The arithmetic instruction is decoded. Then, a first vector register and a second vector register are read from the register file. The present invention then executes the arithmetic instruction on corresponding data elements in the first and second vector registers. The result of the execution is then written into the accumulator. Then, each element in the accumulator is transformed into an N-bit width element and stored into the memory.

Abstract: A system, method and computer program product are provided for texture shading in a hardware graphics processor. Initially, a plurality of texture coordinates is identified. Further, it is determined whether a hardware graphics processor is operating in a texture shader mode. If the hardware graphics processor is operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a plurality of texture shader stages in the hardware graphics processor. If, however, the hardware graphics processor is not operating in the texture shader mode, the texture coordinates are mapped to colors utilizing a conventional graphics application program interface (API) in conjunction with the hardware graphics processor.

Abstract: Method and interface for sending vertex data output from a vertex processing unit to memory is described. Conventionally, the vertex data output is not output directly to memory via a dedicated write interface, but is instead passed through downstream computation units in a graphics processor and written to memory via the write interface normally used to write pixel data. When the downstream computation units are configured to pass the vertex data output through unmodified, processing of the vertex data output by the downstream computation units is deferred until a second pass through those units. When the vertex data output is output directly to memory, processing of the vertex data output by the downstream computation units can be initiated during a first pass through those units.

Abstract: Method and apparatus for shaping a shared edge between two or more N-patches is described. More particularly, vertices and normals of a polygon, tristip, quadstrip and so on, are obtained. Shared vertices corresponding to the shared edge are identified. When normal vectors at a shared vertex are determined to differ, tangents of the normal vectors are computed. These tangents may be used to optionally shape the shared edge, along with control points.

Abstract: System and method for reserving a memory space for multithreaded processing is described. Memory space within a memory resource is allocated responsive to thread type. Examples of thread types for graphics processing include primitive, vertex and fragment types. Memory space allocated may be of a predetermined size for a thread type. Memory locations within a first memory space may be interleaved with memory locations within a second memory space.