Abstract: After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.

Abstract: Semiconductor-on-oxide structures and related methods of forming such structures are disclosed. In one case, a method includes: forming a first dielectric layer over a substrate; forming a first conductive layer over the first dielectric layer, the first conductive layer including one of a metal or a silicide; forming a second dielectric layer over the first conductive layer; bonding a donor wafer to the second dielectric layer, the donor wafer including a donor dielectric and a semiconductor layer; cleaving the donor wafer to remove a portion of the donor semiconductor layer; forming at least one semiconductor isolation region from an unremoved portion of the donor semiconductor layer; and forming a contact to the first conductive layer through donor dielectric and the second dielectric layer.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Abstract: A non-volatile memory device with a programmable leakage can be formed employing a trench capacitor. After formation of a deep trench, a metal-insulator-metal stack is formed on surfaces of the deep trench employing a dielectric material that develops leakage path filaments upon application of a programming bias voltage. A set of programming transistors and a leakage readout device can be formed to program, and to read, the state of the leakage level. The non-volatile memory device can be formed concurrently with formation of a dynamic random access memory (DRAM) device by forming a plurality of deep trenches, depositing a stack of an outer metal layer and a node dielectric layer, patterning the node dielectric layer to provide a first node dielectric for each non-volatile memory device that is thinner than a second node dielectric for each DRAM device, and forming an inner metal layer.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract: A structure forming a metal-insulator-metal (MIM) trench capacitor is disclosed. The structure comprises a multi-layer substrate having a metal layer and at least one dielectric layer. A trench is etched into the substrate, passing through the metal layer. The trench is lined with a metal material that is in contact with the metal layer, which comprises a first node of a capacitor. A dielectric material lines the metal material in the trench. The trench is filled with a conductor. The dielectric material that lines the metal material separates the conductor from the metal layer and the metal material lining the trench. The conductor comprises a second node of the capacitor.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; forming a metal-insulator-metal (MIM) stack within a portion of the deep trench, the MIM stack forming including forming an outer electrode by co-depositing a refractory metal and silicon into the deep trench; and filling a remaining portion of the deep trench with a semiconductor.

Abstract: A deep trench capacitor is provided. The deep trench capacitor may include: a deep trench in a substrate, the deep trench including an lower portion having a width that is wider than a width of the rest of the deep trench; a compressive stress layer against the substrate in the lower portion; a metal-insulator-metal (MIM) stack over the compressive stress layer, the MIM stack including a node dielectric between an inner electrode and an outer electrode; and a semiconductor core within the MIM stack.

Abstract: Method of forming a deep trench capacitor are provided. The method may include forming a deep trench in a substrate; enlarging a width of a lower portion of the deep trench to be wider than a width of the rest of the deep trench; epitaxially forming a compressive stress layer in the lower portion of the deep trench; forming a metal-insulator-metal (MIM) stack within the lower portion of the deep trench; and filling a remaining portion of the deep trench with a semiconductor. Alternatively to forming the compressive stress layer or in addition thereto, a silicide may be formed by co-deposition of a refractory metal and silicon.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: Formation of deep trench capacitors and isolation structures are decoupled by completing the isolation structures prior to etching trenches for capacitors and forming capacitors therein or vice-versa. Such decoupling of the formation of these respective structures allows different materials to be used in the deep trench capacitors and the isolation structures such as use of low permeability or dielectric constant materials and/or low Young's modulus materials in isolation structures to provide reduced AC capacitive coupling across isolation structures and/or relief of stresses associated with use of high dielectric constant materials or metal-insulator-metal (MIM) structures in deep trench capacitors. Such decoupling also allows increased efficiency of use of reaction chambers for the deep trench capacitors and the isolation structures.

Abstract: After formation of trench capacitors and source and drain regions and gate structures for access transistors, a dielectric spacer is formed on a first sidewall of each source region, while a second sidewall of each source region and sidewalls of drain regions are physically exposed. Each dielectric spacer can be employed as an etch mask during removal of trench top dielectric portions to form strap cavities for forming strap structures. Optionally, selective deposition of a semiconductor material can be performed to form raised source and drain regions. In this case, the raised source regions grow only from the first sidewalls and do not grow from the second sidewalls. The raised source regions can be employed as a part of an etch mask during formation of the strap cavities. The strap structures are formed as self-aligned structures that are electrically isolated from adjacent access transistors by the dielectric spacers.

Abstract: Trench capacitors can be formed between lengthwise sidewalls of semiconductor fins, and source and drain regions of access transistors are formed in the semiconductor fins. A dummy gate structure is formed between end walls of a neighboring pair of semiconductor fins, and limits the lateral extent of raised source and drain regions that are formed by selective epitaxy. The dummy gate structure prevents electrical shorts between neighboring semiconductor fins. Gate spacers can be formed around gate structures and the dummy gate structures. The dummy gate structures can be replaced with dummy replacement gate structures or dielectric material portions, or can remain the same without substitution of any material. The dummy gate structures may consist of at least one dielectric material, or may include electrically floating conductive material portions.

Abstract: Embodiments of the invention provide an integrated circuit for an embedded dynamic random access memory (eDRAM), a semiconductor-on-insulator (SOI) wafer in which such an integrated circuit may be formed, and a method of forming an eDRAM in such an SOI wafer.

Abstract: Aspects of the present invention relate to a semiconductor-on-insulator (SOI) deep trench capacitor. One embodiment includes a method of forming a deep trench capacitor structure. The method includes: providing a SOI structure including a first and second trench opening in a semiconductor layer of the SOI structure, forming a doped semiconductor layer covering the semiconductor layer, forming a first dielectric layer covering the doped semiconductor layer, forming a node metal layer over the first dielectric layer, forming a second dielectric layer covering the node metal layer, filling a remaining portion of each trench opening with a metal layer to form an inner node in each of the trench openings, the metal layer including a plate coupling each of the inner nodes, and forming a node connection structure to conductively connect the node metal layer in the first trench opening with the node metal layer in the second trench opening.

Abstract: A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.

Abstract: After formation of semiconductor fins in an upper portion of a bulk semiconductor substrate, a shallow trench isolation layer is formed, which includes a dielectric material and laterally surround lower portions of each semiconductor fin. Trenches are formed between lengthwise sidewalls of neighboring pairs of semiconductor fins. Portions of the shallow trench isolation layer laterally surrounding each trench provide electrical isolation between the buried plate and access transistors. A strap structure can be formed by etching a via cavity overlying a portion of each trench and a source region of the corresponding access transistor, and filling the via cavity with a conductive material. A trench top oxide structure electrically isolates an inner electrode of each trench capacitor from an overlying gate line for the access fin field effect transistor.