Abstract: A non-volatile semiconductor memory device includes a first memory cell above a substrate and electrically connected to a first word line, a second memory cell above the first memory cell and electrically connected to a second word line, and a controller. The controller is configured to execute a write operation that includes a first step in which a first voltage is applied to a selected word line and to a non-selected word line, a second step after the first step in which a program voltage is applied to the selected word line, and a third step after the second step in which a second voltage higher than the first voltage is applied to the non-selected word line. A time period between a start of the second step and a start of the third step is different depending on whether the first or second memory cell is being written.

Abstract: A memory device includes a first memory string including a first selection transistor and a first memory cell, a second memory string including a second selection transistor and a second memory cell, a bit line electrically connected to the first memory string and the second memory string, and a control circuit configured to perform a collective write operation on the first memory cell and the second memory cell by applying a voltage to turn on the first transistor, a voltage to turn on the second transistor, and then a program voltage at the same time to gates of the first and second memory cells.

Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.

Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.

Abstract: A non-volatile semiconductor memory device includes a first memory cell above a substrate and electrically connected to a first word line, a second memory cell above the first memory cell and electrically connected to a second word line, and a controller. The controller is configured to execute a write operation that includes a first step in which a first voltage is applied to a selected word line and to a non-selected word line, a second step after the first step in which a program voltage is applied to the selected word line, and a third step after the second step in which a second voltage higher than the first voltage is applied to the non-selected word line. A time period between a start of the second step and a start of the third step is different depending on whether the first or second memory cell is being written.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.

Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

Abstract: A semiconductor memory device includes a memory cell array including a plurality of groups of memory cells above a substrate, the groups including a first group and a second group, each of the first and second groups including a first memory string and a second memory string, the first memory string including first memory cells that are disposed in a first layer, the second memory string including second memory cell that are disposed in a second layer above the first layer, and a controller configured to perform an erasing operation on the memory cells, the erasing operation including a verifying operation on the memory cells to determine on a layer by layer basis whether the memory cells failed to erase data stored therein.

Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

Abstract: A semiconductor storage device includes a semiconductor substrate, first and second word lines that are stacked above the substrate, extend in a row direction, are electrically connected together, and are separated from each other by a first region, and third and fourth word lines that are stacked above the substrate, extend in the row direction, are electrically connected together, and are separated from each other by a second region. The position of the first region is offset with respect to a position of the second region in the row direction.

Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

Abstract: According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

Abstract: A non-volatile semiconductor device includes first and second selecting transistors; multiple memory cells that are stacked above the substrate; multiple word lines that are connected to control gates of the multiple memory cells; selecting gate lines that are each connected to a gate of one of the selecting transistors; a bit line connected to the first selecting transistor; a source line connected to the second selecting transistor; and a control circuit configured to execute an erasing loop that includes an erase operation and a verifying operation. The control circuit increases an erasing voltage in accordance with the number of times the erasing loop is repeated.

Abstract: According to one embodiment, a semiconductor memory device includes first and second select transistors, memory cells, a driver circuit, first transfer transistors, and a detection circuit. The memory cells are stacked above a semiconductor substrate. The driver circuit outputs a first voltage. The first transfer transistors transfer the first voltage to associated word lines and select gate lines. In data erase, the detection circuit detects a second voltage applied to bit lines and/or a source line and generates a flag in accordance with the detection result. The driver circuit changes the value of the first voltage in response to the flag to cut off the first transfer transistors.

Abstract: A reference voltage generation circuit includes a first node settable at a reference voltage to be any one of a plurality of voltage levels, a second node set at a pre-charge voltage, first and second switches connected in series between the first and second nodes, a plurality of capacitors, each capacitor comprising a first end connected to a connection node between the first and second switches and a second end settable at an independent voltage level, a switch controller configured to turn off the first switch and turn on the second switch in an initial state, and then to turn off the second switch, and then to turn on the first switch, and a voltage controller configured to individually set a voltage at the second end of each capacitor after the first switch is turned on.

Abstract: A power supply circuit has a constant voltage circuit, a first MOS transistor, a second MOS transistor, a third MOS transistor, a first voltage dividing circuit that outputs a first divided voltage obtained by dividing the voltage of the output terminal by a first voltage dividing ratio, and a first differential amplifier circuit which is fed with a reference voltage and the first divided voltage and has an output connected to a gate of the second MOS transistor. The first differential amplifier circuit outputs a signal to turn on the second MOS transistor when the first divided voltage is higher than the reference voltage, and the first differential amplifier circuit outputs a signal to turn off the second MOS transistor when the first divided voltage is lower than the reference voltage.

Abstract: A memory includes ferroelectric capacitors; sense amplifiers configured to detect the data stored in ferroelectric capacitors; and a plate control circuit configured to receive a plate driving signal driving a plate line, a write signal indicating writing of data from an outside to the sense amplifier, and an operation end signal indicating end of an executable period for reading or writing data between the sense amplifier and the outside, the plate control circuit validating or invalidating the plate driving signal based on the write signal and the operation end signal wherein the plate control circuit validates the plate driving signal in the executable period, and the plate control circuit invalidates the plate driving signal at the end of the executable period when the write signal is never activated in the executable period, and keeps the plate driving signal valid when the write signal is activated in the executable period.

Abstract: A ferroelectric memory according to an embodiment of the present invention includes a memory cell array including plural memory cells, and provided with plural word lines, plural bit lines, and plural plate lines, each of the plate lines corresponding to at least two of the word lines, an access control circuit configured to perform an access operation to a selected cell which is selected from the memory cells, and a refresh control circuit configured to perform a refresh operation, in a background of the access operation, on a refresh cell which is selected from the memory cells, the refresh control circuit performing the refresh operation when a plate line connected to the selected cell and a bit line connected to the selected cell are at the same potential after the access operation.

Abstract: A ferroelectric memory of an embodiment of the present invention includes m platelines arranged in a first interconnect layer (m is a positive integer), n bitlines arranged in a second interconnect layer (n is a positive integer), and m×n memory cells arranged at m×n intersection points of the m platelines and the n bitlines, each of the m×n memory cells including a ferroelectric capacitor and a zener diode connected in series between any one of the m platelines and any one of the n bitlines.