Patents by Inventor Hideo Yamamoto

Hideo Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120043604
    Abstract: A semiconductor device includes a semiconductor layer, a first diffused region formed in the semiconductor layer, a second diffused region formed in the first diffused region, a trench formed in the semiconductor layer, a gate electrode disposed in the trench, a top surface of the gate electrode being lower than a top surface of the semiconductor layer and sagging downwards in a center thereof, a non-doped silicate glass film disposed in the trench and formed over the gate electrode, a top surface of the silicate glass film sagging downwards in a center thereof, an oxide film disposed in the trench and formed over the non-doped silicate glass film, a top surface of the oxide film sagging downwards in a center, and a source electrode formed over the semiconductor layer so that the source electrode contacts the first and second diffusion regions, and the oxide film at the top surface thereof.
    Type: Application
    Filed: October 28, 2011
    Publication date: February 23, 2012
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshimitsu MURASE, Kenya KOBAYASHI, Hideo YAMAMOTO, Atsushi KANEKO
  • Publication number: 20120021211
    Abstract: A primary object of the present invention is to provide a laminated sheet for firing having an identification part, the sheet being directly attachable to an adherend, having excellent heat resistance, being free from cracks, etc., during rapid temperature changes such as a rapid temperature increase and rapid water-cooling, and being flexible to follow the change in shape of the adherend. The laminated sheet for firing of the present invention comprises a protective sheet, a temporary adhesion layer, a heat-resistant base layer, a combustible adhesive layer, and a release sheet, which are laminated in this order; the heat-resistant base layer having a thickness of 30 ?m or less, comprising a silicone resin and an inorganic powder, and having the identification part, the identification part being formed from a heat-resistant ink containing an inorganic pigment.
    Type: Application
    Filed: December 22, 2009
    Publication date: January 26, 2012
    Applicant: YUSHI-SEIHIN CO., LTD.
    Inventors: Shoi Nozaki, Hideo Yamamoto, Kenji Takehisa
  • Patent number: 8079078
    Abstract: An encryption apparatus capable of effectively preventing encryption data from being illegally generated is provided. Based on apparatus identification data of an integrated circuit (IC), which is input from a computer, a secure application module (SAM) selects an encryption method from among a plurality of different encryption methods. Based on the code of the IC, the SAM selects plaintext data to be encrypted from among the plurality of different pieces of plaintext data. The SAM outputs encryption data such that the selected plaintext data is encrypted by the selected encryption method.
    Type: Grant
    Filed: December 30, 2004
    Date of Patent: December 13, 2011
    Assignee: Sony Corporation
    Inventors: Hideo Yamamoto, Naofumi Hanaki, Katsuyuki Teruyama, Tomohiko Nagayama, Masahiro Sueyoshi, Yoshiaki Hirano
  • Patent number: 8072026
    Abstract: A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
    Type: Grant
    Filed: March 9, 2010
    Date of Patent: December 6, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Patent number: 8038136
    Abstract: A hand 1 is constituted by a hand base 4 serving as a base portion, a rocking hand 3 disposed to be superposed on the hand base 4 and serving to support a substrate 2, and a rocking mechanism 5 provided between the hand base 4 and the rocking hand 3 and serving to support the rocking hand 3 to be tiltable and movable in parallel with respect to the hand base 4.
    Type: Grant
    Filed: March 20, 2009
    Date of Patent: October 18, 2011
    Assignees: Kabushiki Kaisha Yaskawa Denki, Ebara Corporation
    Inventors: Hiroki Sanemasa, Hideo Yamamoto, Naoomi Torii, Takahiro Ogawa, Seiji Katsuoka, Hidetaka Nakao, Natsuki Makino
  • Patent number: 7980611
    Abstract: A substrate holding apparatus includes a base plate with a two-pronged portion, a holding plate arranged above the base plate, a driving portion provided therebetween, a holding portion formed by a tip end of the two-pronged portion and a tip end of the holding plate, and a guide portion provided at the tip end of the two-pronged portion for guiding a part of the substrate. The driving portion includes an urging means for always urging a basal end side of the holding plate upward, an electric magnetic portion for drawing the holding plate toward the base plate, and a bearing portion arranged at on the tip end side of the base plate. The guide portion has a guide groove which comes into contact with a part of a periphery of the substrate.
    Type: Grant
    Filed: January 23, 2009
    Date of Patent: July 19, 2011
    Assignee: Kabushiki Kaisha Yaskawa Denki
    Inventors: Hideharu Zenpo, Hideo Yamamoto, Toshiyuki Harada, Yoshihiro Kusama, Katsuya Okumura
  • Patent number: 7956409
    Abstract: The present invention provides a vertical MOSFET which has striped trench gate structure which can secure avalanche resistance without increasing Ron. A vertical MOSFET 100 comprises a plurality of gate trenches 7 which is arranged in stripes, an array which is sandwiched with the plurality of gate trenches 7 and includes N+ source regions 4N+ and P+ base contact regions 5P+, and a diode region (anode region 6P+) which is formed so as to contact with two gate trenches 7. The N+ source regions 4N+ and the base contact regions 5P+ are alternately arranged along a longitudinal direction of the gate trench 7. Size of the diode region (anode region 6P+) corresponds to at least one of the N+ source regions 4N+ and two of the P+ base contact regions 5P+.
    Type: Grant
    Filed: September 10, 2008
    Date of Patent: June 7, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Hideo Yamamoto, Kenya Kobayashi, Atsushi Kaneko
  • Patent number: 7947556
    Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
    Type: Grant
    Filed: June 25, 2010
    Date of Patent: May 24, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko, Yoshimitsu Murase
  • Patent number: 7941670
    Abstract: A data processing apparatus is provided which is capable of improving the responsiveness of communication in which only a maximum of one access request source has write authorization and the other access requests do not have write authorization when communication is performed with a plurality of access request sources. A management apparatus transmits, to a secure application module (SAM), a strong connection request requesting the obtainment of write authorization into the SAM. When it is determined that the strong connection has not already been assigned to the other management apparatuses, the SAM assigns the strong connection to the management apparatus in a state in which a weak connection having read authorization with the management apparatuses is maintained.
    Type: Grant
    Filed: May 28, 2009
    Date of Patent: May 10, 2011
    Assignee: Sony Corporation
    Inventors: Masahiro Sueyoshi, Kazuo Omori, Akira Honjo, Naofumi Hanaki, Katsuyuki Teruyama, Tomohiko Nagayama, Hideo Yamamoto, Yuji Hiura, Yoshiaki Hirano
  • Publication number: 20100273304
    Abstract: A method of fabricating a semiconductor device according to the present invention includes forming a first trench and a second trench by etching the first trench further, in an epitaxial layer formed over a substrate, extending a width of the second trench, forming an oxidize film by oxidizing the extended second trench, and filling an electrode material in the first trench and the second trench including the oxidized film formed therein. The method of fabricating a semiconductor device according to the present invention enables to fabricate a semiconductor device that improves the withstand voltage between a drain and a source and reduce the on-resistance.
    Type: Application
    Filed: April 14, 2010
    Publication date: October 28, 2010
    Inventors: Hideo YAMAMOTO, Kei TAKEHARA
  • Publication number: 20100266876
    Abstract: There is provided a fuel cell power generation system in which power loss in a power line electrically connecting a stack and a power conversion circuit, thereby attaining high power generation efficiency. A reformer 6 and the stack 7 are disposed in a main body package 2. Stack output terminals 31 are provided in both ends in a stacking direction of the stack 7. A power conversion circuit 24 is disposed in the main body package 2 and arranged in the proximity to the stack 2. Power conversion circuit input terminals 32 are provided on the power conversion circuit 24 and arrayed in a direction parallel to the stacking direction of the stack. Stack output lines 27 electrically connect the stack output terminals 31 and the power conversion circuit input terminals 32.
    Type: Application
    Filed: December 3, 2008
    Publication date: October 21, 2010
    Applicant: Panasonic Corporation
    Inventor: Hideo Yamamoto
  • Publication number: 20100267211
    Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
    Type: Application
    Filed: June 25, 2010
    Publication date: October 21, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko, Yoshimitsu Murase
  • Patent number: 7812187
    Abstract: An object of the present invention is to provide a method for producing an alkyl ester of a fatty acid from a fat or oil, of which main component is a triglyceride, and an alkyl alcohol under mild conditions in a high reaction efficiency, and the alkyl ester of a fatty acid can be effectively utilized as a diesel fuel oil, an industrial raw material or the like, the method further being capable of utilizing on an industrial scale, in which post-treatment steps for removing a catalyst component can be simplified or omitted. For this purpose, the method for producing an alkyl ester of a fatty acid of this invention includes the step of carrying out a transesterification reaction between a fat or oil and an alcohol in the presence of a base catalyst containing calcium oxide, characterized in that the method includes the step of contacting the base catalyst with the alcohol, to carry out an activation treatment thereof in advance of the reaction.
    Type: Grant
    Filed: January 26, 2007
    Date of Patent: October 12, 2010
    Assignees: Revo International Inc., Ehime University
    Inventors: Ayato Kawashima, Hideo Yamamoto, Tetsuya Koshikawa
  • Patent number: 7776693
    Abstract: A method of manufacturing a semiconductor apparatus includes forming a trench in a semiconductor layer, forming a gate electrode inside the trench, forming a thermally-oxidized film on the gate electrode inside the trench, forming a silicate glass film on the thermally-oxidized film inside the trench, forming a body region inside the semiconductor layer, and forming a source region on the body region. The method provides a semiconductor apparatus having reduced fluctuation of a channel length and low ON-resistance.
    Type: Grant
    Filed: September 27, 2007
    Date of Patent: August 17, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko, Yoshimitsu Murase
  • Publication number: 20100171172
    Abstract: A semiconductor device, includes a semiconductor layer of a second conductive type, a first diffused region of a first conductive type formed in the semiconductor layer, a second diffused region of the second conductive type selectively formed in the first diffused region, a trench formed in the semiconductor layer, a polysilicon formed in the trench with an insulator intervening, a first oxide film formed on the polysilicon so that the first oxide film is buried in the trench, a second oxide film formed on the first oxide film so that the second oxide film is buried in the trench, and a flowable insulator film formed on the second oxide film so that the flowable insulator film is buried in the trench.
    Type: Application
    Filed: March 9, 2010
    Publication date: July 8, 2010
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Patent number: 7705408
    Abstract: A MOSFET has a base layer and a source layer in a cell surrounded by a trench gate formed in a semiconductor substrate. A trench contact is formed through the source layer and the base layer. The gate is polygonal such as square. The trench contact is thin and linear so as to increase embedding characteristics. Further, the trench contact is ring or cross shaped so as to reduce a source length.
    Type: Grant
    Filed: July 29, 2005
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Hideo Yamamoto, Kenya Kobayashi
  • Patent number: 7704827
    Abstract: An epitaxial layer is formed on an n+ semiconductor substrate by epitaxial growth. A gate trench is formed to the surface of gate trench so that the bottom of gate trench reaches middle of the epitaxial layer. A gate insulator is formed on the inner wall of gate trench and a polysilicon is formed in the gate trench with the gate insulator interposed therebetween. An HTO film is formed on the surface of the polysilicon and the n? epitaxial layer. At this time, an ion plantation is performed to the epitaxial layer through the HTO film. Hence, a p diffused base layer, an n+ diffused source layer, an n+ diffused source layer is formed. A CVD oxide film is formed on the HTO film. After a BPSG having flowability is deposited on the CVD oxide film, the BPSG film is planarized with a heat treatment of 900-1100 degree Celsius.
    Type: Grant
    Filed: November 13, 2007
    Date of Patent: April 27, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Yoshimitsu Murase, Kenya Kobayashi, Hideo Yamamoto, Atsushi Kaneko
  • Publication number: 20100044443
    Abstract: A communication apparatus includes: a power generation means for generating drive power to be supplied to individual sections based on an electromagnetic wave transmitted from a reader/writer; a communication means for communicating with the reader/writer in a non-contact manner; an acceleration detection means for detecting an acceleration during generation of the drive power, and converts the detected acceleration to movement information indicative of a moving direction; a storage means for storing the movement information; and a processing means for executing a process according to the moving direction indicated by the stored movement information.
    Type: Application
    Filed: August 18, 2009
    Publication date: February 25, 2010
    Applicant: SONY CORPORATION
    Inventor: Hideo Yamamoto
  • Patent number: D622310
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 24, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Jun Nishiseko, Akira Kosugi, Hideo Yamamoto
  • Patent number: D622313
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: August 24, 2010
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Jun Nishiseko, Akira Kosugi, Hideo Yamamoto