Patents by Inventor Hiroki Nakamura

Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210273386
    Abstract: A receptacle connector 10 includes a ground contact 11 including a fitting portion 11a that has a tubular shape and is to be fitted to a ground contact 101 of a plug connector 100; a signal contact 12 that is to be electrically connected to a signal contact 102 of the plug connector 100; and an insulating housing 13 that holds the ground contact 11 and the signal contact 12 in an insulated state. The signal contact 12 includes a central conductor 12a, and a board connection portion 12b that extends so as to lead out from the central conductor 12a to be connected to a signal terminal portion 201 of the board 200. The board connection portion 12b is accommodated in a region surrounded by the fitting portion 11a, and at least a part of the board connection portion 12b is exposed to an outside.
    Type: Application
    Filed: May 19, 2021
    Publication date: September 2, 2021
    Inventor: Hiroki NAKAMURA
  • Patent number: 10960648
    Abstract: An automotive laminated glass includes a thermoplastic interlayer film, a curved first glass sheet, and a curved second glass sheet. The thermoplastic interlayer film is disposed between the first and second glass sheets. The first glass sheet is a 0.7- to 3-mm thick non-chemically strengthened glass sheet including a convex-side first main surface and a concave-side second main surface facing the thermoplastic interlayer film. The second glass sheet is an ion-exchanged, 0.3- to 1.5-mm thick chemically strengthened glass sheet including a convex-side third main surface facing the thermoplastic interlayer film and a concave-side fourth main surface. The second glass sheet is thinner than the first glass sheet. The convex-side third main surface has a compressive stress layer thicker than that on the concave-side fourth main surface, and the second glass sheet is adjusted to fit the curvature of the first glass sheet.
    Type: Grant
    Filed: November 14, 2017
    Date of Patent: March 30, 2021
    Assignee: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Naoki Mitamura, Tatsuya Tsuzuki, Hiroki Nakamura, Naoya Hirata
  • Patent number: 10937902
    Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.
    Type: Grant
    Filed: May 2, 2018
    Date of Patent: March 2, 2021
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10923591
    Abstract: A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.
    Type: Grant
    Filed: September 30, 2019
    Date of Patent: February 16, 2021
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10825822
    Abstract: In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.
    Type: Grant
    Filed: December 19, 2018
    Date of Patent: November 3, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Min Soo Kim, Zheng Tao
  • Patent number: 10811535
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: May 2, 2016
    Date of Patent: October 20, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10804397
    Abstract: An SGT production method includes a first step of forming a fin-shaped semiconductor layer and a first insulating film; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and etching the third insulating film, the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, subjecting the second polysilicon to etch back to expose the first hard mask, depositing a sixth insulating film, etching the sixth insulating film to form a second hard mask on a side wall of the first hard mask, and etching the second polysilicon to form a second dummy gate.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: October 13, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20200282706
    Abstract: Disclosed is a laminated glass for an automotive vehicle in which a curved first (exterior-side) glass sheet and a curved second (interior-side) glass sheet are opposed to each other with a thermoplastic intermediate film interposed therebetween, wherein a difference in annealing point temperature between the first and second glass sheets is in the range of ±5° C., wherein a difference in softening point temperature between the first and second glass sheets is in the range of ±5° C., wherein the first glass sheet has a glass composition with a FeO content of 0.1 mass % to 0.5 mass %, wherein the second glass sheet has a glass composition with a FeO content of 0 mass % to 0.05 mass %, wherein a thickness of the second glass sheet is 0.5 mm to 1.8 mm, and wherein a thickness of the first glass sheet is 1.1 times to 1.4 times the thickness of the second glass sheet.
    Type: Application
    Filed: September 10, 2018
    Publication date: September 10, 2020
    Inventors: Hiroki NAKAMURA, Naoki MITAMURA, Takuma NAITO
  • Patent number: 10651181
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: May 12, 2020
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura, Phillipe Matagne, Yoshiaki Kikuchi
  • Publication number: 20200122437
    Abstract: An automotive laminated glass includes a thermoplastic interlayer film, a curved first glass sheet, and a curved second glass sheet. The thermoplastic interlayer film is disposed between the first and second glass sheets. The first glass sheet is a 0.7- to 3-mm thick non-chemically strengthened glass sheet including a convex-side first main surface and a concave-side second main surface facing the thermoplastic interlayer film. The second glass sheet is an ion-exchanged, 0.3- to 1.5-mm thick chemically strengthened glass sheet including a convex-side third main surface facing the thermoplastic interlayer film and a concave-side fourth main surface. The second glass sheet is thinner than the first glass sheet. The convex-side third main surface has a compressive stress layer thicker than that on the concave-side fourth main surface, and the second glass sheet is adjusted to fit the curvature of the first glass sheet.
    Type: Application
    Filed: November 14, 2017
    Publication date: April 23, 2020
    Applicant: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Naoki Mitamura, Tatsuya Tsuzuki, Hiroki Nakamura, Naoya Hirata
  • Publication number: 20200066904
    Abstract: A method for producing an SGT employs a gate-last process that includes forming a fin-shaped semiconductor layer, a pillar-shaped semiconductor layer, a gate electrode, and a gate line by self-alignment. The gate line and the pillar-shaped semiconductor layer are formed in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends.
    Type: Application
    Filed: September 30, 2019
    Publication date: February 27, 2020
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 10551658
    Abstract: An image display apparatus that that can easily separate an image display apparatus from a touch panel. The image display apparatus comprises a liquid crystal panel (image display apparatus main body), a touch panel that has a fine, uneven structure on its surface and faces the liquid crystal panel via a gap, and an adhesive member for securing these, the adhesive member comprising a substrate, a first adhesive layer, and a second adhesive layer, wherein an adhesive strength (W1) between the first adhesive layer and the liquid crystal panel is less than an adhesive strength (W3) of the first adhesive layer and the substrate, an adhesive strength (W3?) of the second adhesive layer and the substrate, and an adhesive strength (W5) of the second adhesive layer and the touch panel, and wherein a breaking strength (W4) of the substrate is greater than W3? and/or W5.
    Type: Grant
    Filed: December 10, 2015
    Date of Patent: February 4, 2020
    Assignee: Mitsubishi Chemical Corporation
    Inventors: Atsushi Saiki, Hiroki Nakamura
  • Publication number: 20190372980
    Abstract: Provided are a program execution control method capable of preventing a malicious third party from misappropriating a web application program, a program, a recording medium, a web page, a transmission server, a client, and a web system. In the program execution control method, the program, the recording medium, the web page, the transmission server, the client, and the web system, the web application program includes a list of identification information of authorized servers written by a low-level language, a determination program, and a processing program which are written by a low-level language. The determination program checks whether identification information of the transmission server extracted from a URI of a web page and identification information of an authorized server included in the list match each other, and limits execution of the processing program according to the check result.
    Type: Application
    Filed: May 30, 2019
    Publication date: December 5, 2019
    Applicant: FUJIFILM Corporation
    Inventors: Hiroki NAKAMURA, Hironori YANO
  • Publication number: 20190358935
    Abstract: An automotive laminated glass includes a thermoplastic interlayer film, a curved first glass sheet, and a curved second glass sheet. The thermoplastic interlayer film is disposed between the first and second glass sheets. The first glass sheet is a 0.7- to 3-mm thick non-chemically strengthened glass sheet including a convex-side first main surface and a concave-side second main surface facing the thermoplastic interlayer film. The second glass sheet is an ion-exchanged, 0.3- to 1.5-mm thick chemically strengthened glass sheet including a convex-side third main surface facing the thermoplastic interlayer film and a concave-side fourth main surface. The second glass sheet is thinner than the first glass sheet, and is adjusted to have a curvature equal to the curvature of the first glass sheet. A compressive stress layer on the concave-side fourth main surface is thicker than a compressive stress layer on the convex-side third main surface.
    Type: Application
    Filed: November 14, 2017
    Publication date: November 28, 2019
    Applicant: CENTRAL GLASS COMPANY, LIMITED
    Inventors: Naoki Mitamura, Tatsuya Tsuzuki, Hiroki Nakamura, Naoya Hirata
  • Patent number: 10490681
    Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a planar semiconductor layer, a first insulator surrounding the pillar-shaped semiconductor layer, a first gate surrounding the first insulator and made of a metal having a first work function, a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, a third gate surrounding the first insulator and made of a metal having the first work function, a first metal layer surrounding the first insulator and having a third work function, and a second metal layer surrounding the first insulator and having the third work function. The first gate, the second gate, and the third gate are electrically connected together.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: November 26, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10483376
    Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
    Type: Grant
    Filed: July 24, 2019
    Date of Patent: November 19, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura, Nozomu Harada
  • Patent number: 10483366
    Abstract: A semiconductor device includes a third first-conductivity-type semiconductor layer on a semiconductor substrate, and a first pillar-shaped semiconductor layer on the semiconductor substrate. The first pillar-shaped semiconductor layer including a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, a second second-conductivity-type semiconductor layer, and a third second-conductivity-type semiconductor layer. A first gate insulating film is around the first body region, and a first gate is around the first gate insulating film. A second gate insulating film is around the second body region and a second gate is around the second gate insulating film. An output terminal is connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer, and a first contact connects the first gate and the second gate.
    Type: Grant
    Filed: August 18, 2017
    Date of Patent: November 19, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20190348526
    Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
    Type: Application
    Filed: July 24, 2019
    Publication date: November 14, 2019
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Nozomu HARADA
  • Patent number: 10475922
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.
    Type: Grant
    Filed: November 1, 2017
    Date of Patent: November 12, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: D885021
    Type: Grant
    Filed: November 1, 2018
    Date of Patent: May 26, 2020
    Assignee: FIL LIMITED
    Inventor: Hiroki Nakamura