Patents by Inventor Hiroki Nakamura
Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20180248038Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.Type: ApplicationFiled: May 2, 2018Publication date: August 30, 2018Inventors: Fujio MASUOKA, Hiroki NAKAMURA
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Patent number: 10056483Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the fin-shaped semiconductor layer, and a first metal film is formed around the first insulating film. A pillar-shaped semiconductor layer is formed on the fin-shaped semiconductor layer and a gate insulating film is formed around the pillar-shaped semiconductor layer. A gate electrode is formed around the gate insulating film, the gate electrode being made of a third metal, and a gate line is connected to the gate electrode. A second insulating film is formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film is formed around the second insulating film.Type: GrantFiled: August 9, 2017Date of Patent: August 21, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10056471Abstract: A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate electrode and extends in a direction perpendicular to a direction that of the fin-shaped semiconductor layer. A width of a bottom of the pillar-shaped semiconductor layer in a direction parallel to a direction in which the metal gate line extends is equal to a width of a top of the fin-shaped semiconductor layer in the direction parallel to the direction of the metal gate line. A gate insulating film is in contact with an underside of the gate electrode and the gate line and separates the metal gate electrode and the metal gate line from the fin-shaped semiconductor layer and a first insulating film. An outer width of the metal gate electrode is equal to a width of the metal gate line.Type: GrantFiled: November 3, 2016Date of Patent: August 21, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10026893Abstract: A method for producing a memory device includes depositing a second interlayer insulating film on a substrate, forming contact holes, and depositing a second metal and a nitride film. The second metal and the nitride film are removed to form pillar-shaped nitride layers, and to form lower electrodes surrounding the pillar-shaped nitride layers. The second interlayer insulating film is etched back to expose upper portions of the lower electrodes. The upper portions of the lower electrodes surrounding the pillar-shaped nitride film are removed and a phase change film is deposited to surround the pillar-shaped nitride film and connect with the lower electrodes. The phase change film is etched on upper portions of the pillar-shaped nitride film, and a reset gate insulating film is formed surrounding the phase change film and forming a reset gate having a side wall shape and remaining on the upper portions of the pillar-shaped nitride film.Type: GrantFiled: July 12, 2017Date of Patent: July 17, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10026739Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer in which a second first-conductivity-type semiconductor layer, a first body region, a third first-conductivity-type semiconductor layer, a fourth first-conductivity-type semiconductor layer, a second body region, a fifth first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a third body region, and a second second-conductivity-type semiconductor layer are formed from a substrate side in this order; first, second, and third gates formed around first, second, third gate insulating films formed around the first, second, and third body regions, respectively; a first output terminal connecting the fifth first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; a second pillar-shaped semiconductor layer, on the first output terminal, in which a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-typType: GrantFiled: June 1, 2017Date of Patent: July 17, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10026842Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate; a third step of forming a second dummy gate; a fourth step of forming a fifth insulating film and a sixth insulating film; a fifth step of depositing a first interlayer insulating film, removing the second dummy gate and the first dummy gate, forming a gate insulating film, depositing metal, and performing etch back to form a gate electrode and a gate line; a seventh step of forming a seventh insulating film; and an eighth step of forming insulating film sidewalls, forming a first epitaxially grown layer on the fin-shaped semiconductor layer, and forming a second epitaxially grown layer on the pillar-shaped semiconductor layer.Type: GrantFiled: July 13, 2017Date of Patent: July 17, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 10008595Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating fType: GrantFiled: September 13, 2016Date of Patent: June 26, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Publication number: 20180175047Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.Type: ApplicationFiled: February 15, 2018Publication date: June 21, 2018Inventors: Fujio MASUOKA, Hiroki NAKAMURA
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Patent number: 10002934Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.Type: GrantFiled: January 22, 2015Date of Patent: June 19, 2018Assignee: Unisantis Electronics Singapore Pte. Ltd.Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura
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Patent number: 10002963Abstract: A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a first metal film around the first insulating film. A pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer, and a gate insulating film is around the pillar-shaped semiconductor layer. A gate electrode is around the gate insulating film and is made of a third metal. A gate line is connected to the gate electrode, and an upper portion of the fin-shaped semiconductor layer and the first metal film are electrically connected to each other.Type: GrantFiled: August 9, 2017Date of Patent: June 19, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9991381Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.Type: GrantFiled: July 13, 2015Date of Patent: June 5, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Publication number: 20180138294Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.Type: ApplicationFiled: December 20, 2017Publication date: May 17, 2018Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Nozomu HARADA
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Patent number: 9972722Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating fType: GrantFiled: September 13, 2016Date of Patent: May 15, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Publication number: 20180122940Abstract: A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.Type: ApplicationFiled: December 29, 2017Publication date: May 3, 2018Inventors: Fujio MASUOKA, Hiroki NAKAMURA
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Patent number: 9960277Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.Type: GrantFiled: November 28, 2017Date of Patent: May 1, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9954032Abstract: A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.Type: GrantFiled: July 6, 2017Date of Patent: April 24, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Patent number: 9947670Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.Type: GrantFiled: June 18, 2015Date of Patent: April 17, 2018Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.Inventors: Fujio Masuoka, Hiroki Nakamura
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Publication number: 20180089933Abstract: A game system of the present invention is configured to move a character image displayed in said display area of the single display, after the game on the game devices are interrupted, the character image being for indicating the game device to receive the prize, and stop the character image on the display of the game device to receive the prize, after a predetermined period from the beginning of moving the character image.Type: ApplicationFiled: April 21, 2017Publication date: March 29, 2018Inventors: Kenji ENOKIDO, Hiroki NAKAMURA, Ken YOSHIKAWA, Yukihiro KAWAKAMI
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Publication number: 20180089934Abstract: A display state in which the specific symbol is displayed in all the rows of any of N columns continuously from one side of a symbol matrix to another side, a prize of the rank corresponding to the columns with the specific symbols displayed on all the rows of the columns is awarded.Type: ApplicationFiled: April 21, 2017Publication date: March 29, 2018Inventors: Kenji ENOKIDO, Hiroki NAKAMURA, Ken YOSHIKAWA, Yukihiro KAWAKAMI
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Publication number: 20180090623Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.Type: ApplicationFiled: November 28, 2017Publication date: March 29, 2018Inventors: Fujio MASUOKA, Hiroki NAKAMURA