Patents by Inventor Hiroki Nakamura

Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10438836
    Abstract: A method for manufacturing a semiconductor device includes etching a semiconductor substrate to form a fin-shaped semiconductor layer. After forming the fin-shaped semiconductor layer, a first insulating film is deposited around the fin-shaped semiconductor layer. The first insulating film is etched back to expose an upper portion of the fin-shaped semiconductor layer and a second resist is formed so as to be perpendicular to the fin-shaped semiconductor layer. The fin-shaped semiconductor layer is etched to form a pillar-shaped semiconductor layer, such that a portion where the fin-shaped semiconductor layer and the second resist intersect at right angles defines the pillar-shaped semiconductor layer.
    Type: Grant
    Filed: July 27, 2016
    Date of Patent: October 8, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10422060
    Abstract: A holding material including: inorganic fibers that include 70 wt % or more of an alumina component an organic binder other than polyacrylamide of which the surface is negatively charged, alumina sol, and polyacrylamide having a weight-average molecular weight of 3,000,000 to 6,000,000, wherein the amount of the alumina sol is 2 to 8 parts by weight relative to 100 parts by weight of the amount of the inorganic fibers, and the amount of the polyacrylamide is 0.01 to 1.0 parts by weight relative to 100 parts by weight of the amount of the inorganic fibers.
    Type: Grant
    Filed: February 25, 2016
    Date of Patent: September 24, 2019
    Assignee: NICHIAS CORPORATION
    Inventors: Akihiro Nakashima, Kazutoshi Isomura, Hiroki Nakamura, Yuki Takeda
  • Patent number: 10417876
    Abstract: A gaming machine that is capable of providing information relevant to a winning combination to a player before spinning of a respective one of reels stops in a unit game is provided. When the player's operation is made, in the case where the predetermined symbol is displayed in the effect reel display region 410, symbol arrays of the effect reels are scrolled in an upward direction or in a downward direction and then the predetermined symbol is displayed at the to-be-stopped position, or alternatively, in the case where the predetermined symbol is not displayed, scrolling is controlled so that a symbol displayed immediately after the above situation is replaced with the predetermined symbol and then the predetermined symbol appears from an upper part of the effect reel display region 410, and stops at the to-be-stopped position.
    Type: Grant
    Filed: April 21, 2014
    Date of Patent: September 17, 2019
    Assignees: UNIVERSAL ENTERTAINMENT CORPORATION, ARUZE GAMING AMERICA, INC.
    Inventors: Masumi Fujisawa, Hiroki Nakamura, Takeshi Narita, Hiromoto Yamauchi
  • Patent number: 10411021
    Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
    Type: Grant
    Filed: February 15, 2018
    Date of Patent: September 10, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10399303
    Abstract: A resin-coated metal sheet for can lids includes a metal sheet coated with thermoplastic resin films on both surfaces and formed into a can lid. A thermoplastic resin film A based on polybutylene terephthalate (PBT) and polyethylene terephthalate (PET) is heat-fused on a surface of the metal sheet serving as an exterior surface of the can lid, and a thermoplastic resin film B based on polyethylene terephthalate (PET) is heat-fused on a surface of the metal sheet serving as an interior surface of the can lid. A composition ratio (wt %) of PBT/PET in the thermoplastic resin film A on the exterior surface is (PBT/PET)=(40/60) to (80/20), and the thermoplastic resin film B on the interior surface includes 95 mol % or more of PET.
    Type: Grant
    Filed: December 8, 2015
    Date of Patent: September 3, 2019
    Assignee: JFE STEEL CORPORATION
    Inventors: Norihiko Nakamura, Yoichiro Yamanaka, Junichi Kitagawa, Hiroki Nakamura, Hiroshi Kubo, Yusuke Nakagawa
  • Patent number: 10396197
    Abstract: A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.
    Type: Grant
    Filed: December 29, 2017
    Date of Patent: August 27, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10381451
    Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.
    Type: Grant
    Filed: October 19, 2017
    Date of Patent: August 13, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20190237367
    Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.
    Type: Application
    Filed: April 2, 2019
    Publication date: August 1, 2019
    Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Phillipe MATAGNE, Yoshiaki KIKUCHI
  • Patent number: 10340184
    Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.
    Type: Grant
    Filed: December 21, 2018
    Date of Patent: July 2, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20190148387
    Abstract: In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.
    Type: Application
    Filed: December 19, 2018
    Publication date: May 16, 2019
    Inventors: Fujio MASUOKA, Nozomu HARADA, Hiroki NAKAMURA, Min Soo KIM, Zheng TAO
  • Publication number: 20190148228
    Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.
    Type: Application
    Filed: December 21, 2018
    Publication date: May 16, 2019
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 10247077
    Abstract: A retention material for a gas processing device including a processing structure and a casing for accommodating the processing structure, the retention material including inorganic fibers and being arranged between the processing structure and the casing, wherein in a test of repeating a cycle of compressing the retention material until a bulk density of the retention material becomes a prescribed compression bulk density, followed by retaining for 10 seconds, and then releasing until a bulk density of the retention material becomes a release bulk density that is smaller by 12% of said prescribed compression bulk density; a release surface pressure of the retention material after repeating the cycle 2500 times and the compression bulk density of the retention material satisfies the relationship, P?17.10×D?1.62 wherein P is the release surface pressure (N/cm2) and D is the compression bulk density (g/cm3).
    Type: Grant
    Filed: March 24, 2014
    Date of Patent: April 2, 2019
    Assignee: NICHIAS CORPORATION
    Inventors: Hiroki Nakamura, Nobuya Tomosue, Tadashi Sakane
  • Patent number: 10217665
    Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer formed on a semiconductor substrate; a first first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer; a third first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer and located at a higher position than the first first-conductivity-type semiconductor layer; a first gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; a first gate formed so as to surround the first gate insulating film; a second gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; and a second gate formed so as to surround the secon
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: February 26, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10186601
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.
    Type: Grant
    Filed: November 3, 2016
    Date of Patent: January 22, 2019
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 10138775
    Abstract: A holding material includes a stack of a first mat and a second mat, the first mat including alumina fibers that include 60 wt % or more of alumina and 40 wt % or less of silica, and the second mat including silica fibers that include 60 wt % or more of silica and 40 wt % or less of alumina and having a surface pressure higher than that of the first mat as measured at a gap bulk density of 0.30 g/cm3.
    Type: Grant
    Filed: June 11, 2015
    Date of Patent: November 27, 2018
    Assignee: NICHIAS CORPORATION
    Inventors: Kazutoshi Isomura, Hiroki Nakamura, Kiyoshi Sato, Isami Abe
  • Publication number: 20180248038
    Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.
    Type: Application
    Filed: May 2, 2018
    Publication date: August 30, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 10056483
    Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the fin-shaped semiconductor layer, and a first metal film is formed around the first insulating film. A pillar-shaped semiconductor layer is formed on the fin-shaped semiconductor layer and a gate insulating film is formed around the pillar-shaped semiconductor layer. A gate electrode is formed around the gate insulating film, the gate electrode being made of a third metal, and a gate line is connected to the gate electrode. A second insulating film is formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film is formed around the second insulating film.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: August 21, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: D838093
    Type: Grant
    Filed: October 10, 2017
    Date of Patent: January 15, 2019
    Assignee: Cubism Inc.
    Inventor: Hiroki Nakamura
  • Patent number: D850067
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: June 4, 2019
    Assignee: CUBISM INC.
    Inventor: Hiroki Nakamura
  • Patent number: D855296
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: August 6, 2019
    Assignee: CUBISM INC.
    Inventor: Hiroki Nakamura