Abstract: A method of producing a lens molded article includes a state determination of determining, after molding the lens molded article, whether a state is a first state where the lens molded article molded remains in an upper mold or a second state where the lens molded article molded remains in a lower mold; an adsorption of adsorbing an exposed surface of the lens molded article remaining in the upper mold or the lower mold, by an adsorption device disposed at an arm of a molded article moving device; an adsorption surface change of changing an adsorption surface from a surface adsorbed by the adsorption device to an opposite surface to the exposed surface when the determination result in the state determination is either one of the first state or the second state; and a placement of placing on a tray the lens molded article adsorbed by the adsorption device.

Abstract: As a first aspect, provided is a hybrid lens for which peeling and shifting of a glass and a resin lens do not easily occur, and for which floating of an adhesive layer and peeling between the glass and resin lens do not easily occur even when the hybrid lens is exposed to a high temperature environment. As a second aspect, provided is an easily produced hybrid lens in which a glass and a resin lens are laminated, and in which the resin lens and a light-shielding portion are laminated with good precision. The hybrid lenses 11 and 12 each include a glass substrate 3, a resin lens 2, and an adhesive layer 4 provided between the glass substrate 3 and the resin lens 2. In the hybrid lens 11, the glass transition temperature of the resin lens 2 is higher than the glass transition temperature of the adhesive layer 4, and the difference between the glass transition temperature of the resin lens 2 and the glass transition temperature of the adhesive layer 4 is from 97 to 150° C.

Abstract: The imaging-device lens module includes a lens and a spacer. The lens includes a functioning portion, a non-functioning portion, and a support. The non-functioning portion is disposed around the periphery of, and is integral with, the functioning portion. The support is integral with the non-the functioning portion and supports the lens. The spacer has a flat top face, and the support has a flat bottom face. The spacer is bonded at the top face to the bottom face to support the lens. The top face has a width B, and the bottom face has a width A, where B is greater than A. The support has a height L1, the spacer has a height L2, and the functioning portion has a diameter D, where the total of L1 and L2 is greater than D, and where the diameter D is equal to or greater than the height L1.

Abstract: Provided is an imaging-device lens module that can employ a lens having high form accuracy even with a long focal length, enables easy adjustment of the focal length with a small number of parts, and enables easy adjustment of the focal position before joining of the lens and a spacer. The imaging-device lens module includes a lens 1, a spacer 2, and a substrate 3 including a photodetector 3a. The lens 1 includes a functioning portion 1a, a non-functioning portion 1b, and a support 1c. The non-functioning portion 1b is disposed around the periphery of, and is integral with, the functioning portion 1a. The support 1c is integral with the non-the functioning portion 1a and supports the lens 1. The spacer 2 has a flat top face 2a, and the support 1c has a flat bottom face 1d. The spacer 2 is bonded at the top face 2a to the bottom face 1d to support the lens 1. The top face 2a has a width B, and the bottom face 1d has a width A, where B is greater than A.

Abstract: A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing dock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.

Abstract: A Viterbi detector includes an ACS circuit that performs addition of a path metric and branch metrics, comparison of the path metric values and path selection based on the result of comparison. The ACS circuit performs a path decision based on the path metric values and the reproduced signal supplied to the Viterbi detector at the time instant that is a specified number of channel clocks earlier during the path selection. The ACS circuit selects a mark-continuing path if the reproduced signal at the time instant that is the specified number of channel clocks earlier has an amplitude corresponding to any mark, and performs path decision based on the path metric values if the reproduced signal does not have the amplitude corresponding to any mark.

Abstract: A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.

Abstract: An offset corrector of an information readout apparatus receives a digital signal DRF output from an A/D converter, and performs offset correction. The offset corrector is capable of switching between a level-correction operation that corrects the offset so that the DC level of the shortest period signal included in the readout signal assumes a zero amplitude reference and a HPF operation that matches the level of the readout signal with the zero amplitude reference. The offset corrector corrects the offset in the level correction operation during a normal reproduction, and switches to the HPF operation for offset correction when a defect judgment unit detects a defective area. The information readout apparatus is stable and has a superior performance without a symmetry deviation if there occurs a waveform fluctuation caused by a defect etc.

Abstract: An information detection device includes an equalizer that equalizes the readout signal to a PR channel having equalization target levels of four or more values, and a Viterbi detector. The Viterbi detector generates branch metrics with the equalization target levels as reference levels to determine recording data from an output of the equalizer. The Viterbi detector has a mode of generating the branch metrics and determining the recording data by limiting at least one out of a maximum value and a minimum value of the equalization target levels.

Abstract: A digital PLL (phase locked loop) circuit (and method thereof), includes an AAF (anti aliasing filter) that limits a frequency bandwidth of an input RF (radio frequency) signal on the basis of a given cutoff frequency, an ADC (analog to digital converter) that samples an output signal of the AAF on the basis of a given sampling frequency, a down converter that converts a data rate of the ADC, and a digital phase tracking unit that generates a synchronous clock signal from an output signal of the down converter on the basis of a given internal frequency. The cutoff frequency and the sampling frequency are fixed, respectively, even when a frequency bandwidth of the RF signal fluctuates. The down converter reduces the data rate according to an increase in the frequency bandwidth of the RF signal.

Abstract: An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.

Abstract: An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.

Abstract: An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency.

Abstract: An optical disc device includes an optical head section and a regularity monitoring circuit. The optical head section generates a wobble signal indicating wobbling of a track formed on a recording surface of an optical disc medium based on a reflected light reflected by the optical disc medium. The regularity monitoring circuit judges an existence or absence of a defect on the optical disc medium based on a difference between the wobble signal and a signal indicating the wobble under a normal condition.

Abstract: An information detection device includes an equalizer that equalizes the readout signal to a PR channel having equalization target levels of four or more values, and a Viterbi detector. The Viterbi detector generates branch metrics with the equalization target levels as reference levels to determine recording data from an output of the equalizer. The Viterbi detector has a mode of generating the branch metrics and determining the recording data by limiting at least one out of a maximum value and a minimum value of the equalization target levels.

Abstract: An LPP detection unit detects an LPP from a wobble signal. A correction unit obtains a difference set by performing processing of calculating a difference in signal level between an LPP-present sync pattern portion and a non-LPP sync pattern portion having the same polarity, and executes correction on an RF signal at a timing when the LPP is detected, by using the difference set. The LPP-present sync pattern portion is a sync pattern portion obtained when the LPP is detected at the timing of the sync pattern portion positioned at the head of a sync frame of the RF signal. The non-LPP sync pattern portion is a sync pattern portion obtained when no LPP is detected at the timing of the sync pattern portion of the sync frame. In the case of reproducing information recorded on a DVD-R/RW optical disk, the occurrence of errors due to the effect of the LPP can be reduced.

Abstract: An adaptive equalizer includes: an equalizer configured to equalize a digital RF signal based on a plurality of tap coefficients; and a tap coefficient controller configured to correct the plurality of tap coefficients in a time division. The tap coefficient controller includes a tap coefficient register configured to hold the plurality of tap coefficients; and a product-sum calculating circuit configured to correct at least one selected from the plurality of tap coefficients in response to an enable signal, by a predetermined product-sum calculation, and update the selected tap coefficient by the corrected tap coefficient.

Abstract: A Viterbi detector includes an ACS circuit that performs addition of a path metric and branch metrics, comparison of the path metric values and path selection based on the result of comparison. The ACS circuit performs a path decision based on the path metric values and the reproduced signal supplied to the Viterbi detector at the time instant that is a specified number of channel clocks earlier during the path selection. The ACS circuit selects a mark-continuing path if the reproduced signal at the time instant that is the specified number of channel clocks earlier has an amplitude corresponding to any mark, and performs path decision based on the path metric values if the reproduced signal does not have the amplitude corresponding to any mark.

Abstract: A digital loop filter receives a phase error output from a phase comparator to generate a digital frequency value. This digital frequency value is converted into an analog voltage by a D/A converter, and VCO outputs a synchronizing clock of frequency corresponding to the voltage output from the D/A converter. The phase error output from a phase comparator is gain-corrected by a product of an output from the digital loop filter and a specific coefficient “A”, and delivered to digital loop filter. The phase error input to the digital loop filter is changed in proportion to the output clock frequency, whereby the PLL loop as whole linearly controls the loop characteristic depending on the output clock frequency.

Abstract: An offset corrector of an information readout apparatus receives a digital signal DRF output from an A/D converter, and performs offset correction. The offset corrector is capable of switching between a level-correction operation that corrects the offset so that the DC level of the shortest period signal included in the readout signal assumes a zero amplitude reference and a HPF operation that matches the level of the readout signal with the zero amplitude reference. The offset corrector corrects the offset in the level correction operation during a normal reproduction, and switches to the HPF operation for offset correction when a defect judgment unit detects a defective area. The information readout apparatus is stable and has a superior performance without a symmetry deviation if there occurs a waveform fluctuation caused by a defect etc.