Abstract: An A/D converter samples a read signal in synchrony with a system clock sclk having a fixed frequency, to perform an A/D conversion. A fluctuation compensator is configured as an internal-feedback-type compensation filter, and suppresses fluctuation of a digital signal output from the A/D converter. A digital PLL uses an interpolator to generate, by interpolation, a sampled value of the read signal at a timing in synchrony with a channel frequency, and uses NCO to generate a synchronizing clock and an interpolated-phase signal that is fed back to the interpolator. A binarization circuit binarizes the read signal based on the interpolated value output from the interpolator. The frequency characteristic of the fluctuation compensator is controlled based on the frequency value output from the loop filter.

Abstract: An information readout apparatus includes analog to digital converting means, equalizing means, interpolating means, maximum likelihood detecting means and PLL means. The analog to digital converting means converts a read signal read out from an optical disc medium, on which data is recorded with run length limited code that the shortest run length is 1, into a digital signal, and outputs the digital signal in synchronous with a first clock signal with a frequency which is N/M times of a channel frequency. At this time, N is an integer equal to or more than 2 and M is an integer meeting N/M>0.5. The equalizing means equalizes said digital signal to a previously specified partial response (PR) characteristic in synchronous with said first clock signal signal. The interpolating means converts N input data outputted from said equalizing means into M output data, and outputs output data in synchronous with a second clock signal with a frequency of 1/M times of the channel frequency.

Abstract: Reproduced signals are equalized by the least square technique by using a predetermined number of data samples binarized by a Viterbi decoder. Even when data written on an optical disk is unknown, the data can be equalized in a stable manner and can be reproduced at a low error rate without instability factors such as divergence due to interference.

Abstract: An optical disc device includes an optical head section and a regularity monitoring circuit. The optical head section generates a wobble signal indicating wobbling of a track formed on a recording surface of an optical disc medium based on a reflected light reflected by the optical disc medium. The regularity monitoring circuit judges an existence or absence of a defect on the optical disc medium based on a difference between the wobble signal and a signal indicating the wobble under a normal condition.

Abstract: A data reproducing apparatus includes a data pulse generating section and a detector section which converts a readout signal reproduced from a data recording medium into a binary data in synchronization with the readout signal to output the binary data as a pulsed output signal. The detector section outputs a determination result indicating whether or not the data pulse generating section is in asynchronization, to the data pulse generating section based on the pulsed output signal. When the determination result indicates the asynchronization, the data pulse generating section sets a predetermined fixed operation parameter and carries out a recovering operation from the asynchronization.

Abstract: In order to evaluate the quality of a signal recorded on an optical recording medium, a target signal is obtained based on a predetermined data string and a predetermined partial response characteristic, and for each clock cycle, an equalization error is calculated that is a difference between the target signal and a signal reproduced each clock cycle. Further, the product of the equalization errors calculated at different times is obtained, and based on the obtained product, the quality of a signal is evaluated.

Abstract: An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.

Abstract: A VCO, which good temperature characteristics, high frequency accuracy, and high phase accuracy is provided as an LSI, without making its master clock frequency operate the VCO high. The VCO includes a digital VCO, a phase modulator, and a frequency band limiting element. The digital VCO outputs an oscillating frequency clock and a phase difference lower than an output cycle resolution at the same timing as the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from positions near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference.

Abstract: A recording state detection system includes a Viterbi detection unit, an error calculation unit for calculating error data series representing a difference between each sample data of the reproduced data series and a corresponding data of the data series output from the Viterbi detection unit, a normal level judgement unit for judging the normal level of each sample data, and a state calculation unit for calculating the amplitude data and the asymmetry of the sample data series based on the error data series and the normal level. The disk drive unit corrects a recording optical power based on the calculated amplitude and the asymmetry.

Abstract: An A/D converter includes a low-bit resolution A/D which converts an input signal into a digital value of 4 bits or less, and a low-pass digital filter which suppresses a high-frequency-band component in an output from the low-bit resolution A/D, and extracts phase information contained in the input signal as amplitude information. A digital PLL circuit and information recording apparatus are also disclosed.

Abstract: Reproduced signals are equalized by the least square technique by using a predetermined number of data samples binarized by a Viterbi decoder. Even when data written on an optical disk is unknown, the data can be equalized in a stable manner and can be reproduced at a low error rate without instability factors such as divergence due to interference.

Abstract: In order to evaluate the quality of a signal recorded on an optical recording medium, a target signal is obtained based on a predetermined data string and a predetermined partial response characteristic, and for each clock cycle, an equalization error is calculated that is a difference between the target signal and a signal reproduced each clock cycle. Further, the product of the equalization errors calculated at different times is obtained, and based on the obtained product, the quality of a signal is evaluated.

Abstract: A PLL circuit is disclosed which extracts phase difference information of a high S/N ratio from a readout signal uses the phase difference information for PLL control. An A/D converter samples the input signal to produce a digital signal. A pattern string detector identifies a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputs pattern string identification information which indicates an identification result. A phase difference generator outputs phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter. A loop filter, a D/A converter and a voltage controlled oscillator generate a clock signal from the phase difference information to control the sampling timing of the A/D converter.

Abstract: In an information detecting circuit, an equalizer equalizes an output from an A/D converter as an A/D converting information. A first interpolation circuit generates an interpolating value. A delay circuit delays the A/D converting information with a delay quantity equivalent to an output delay quantity of the equalizer. A second interpolation circuit generates an interpolating value. An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock and supplies the interpolating position information into the first interpolation circuit and the second interpolation circuit. A binary encoder converts the output of the first interpolation circuit. A tap coefficient controller generates a tap coefficient from interpolating value outputs of the first and second interpolations. A rate correcting circuit converts the tap coefficient to be fed-back to the equalizer.

Abstract: A VCO, in which its temperature characteristics are good and its high frequency accuracy and high phase accuracy can be realized without making its master clock frequency to operate the VCO high and its circuit can be realized as an LSI, is provided. Further, a PLL circuit using this VCO and a data recording apparatus using this PLL circuit are provided. The VCO provides a digital VCO, a phase modulator, and a frequency band limiting means. The digital VCO outputs an oscillating frequency clock and phase difference being lower than output cycle resolution at the same timing of the output of the oscillating frequency clock. The phase modulator makes side-band components of the output from the digital VCO move from the position near the fundamental frequency to farther bands by modulating the phase of the output from the digital VCO based on the phase difference. The frequency band limiting means such as a BPF eliminates the side-band components moved to the farther bands.

Abstract: A recording state detection system includes a Viterbi detection unit, an error calculation unit for calculating error data series representing a difference between each sample data of the reproduced data series and a corresponding data of the data series output from the Viterbi detection unit, a normal level judgement unit for judging the normal level of each sample data, and a state calculation unit for calculating the amplitude data and the asymmetry of the sample data series based on the error data series and the normal level. The disk drive unit corrects a recording optical power based on the calculated amplitude and the asymmetry.

Abstract: A PLL circuit is disclosed which extracts phase difference information of a high S/N ratio from a readout signal uses the phase difference information for PLL control. An A/D converter samples the input signal to produce a digital signal. A pattern string detector identifies a type of an input pattern string formed from a plurality of successive sample values successively outputted from the A/D converter and outputs pattern string identification information which indicates an identification result. A phase difference generator outputs phase difference information which indicates a phase error of the output of the A/D converter based on the pattern string identification information and the output of the A/D converter. A loop filter, a D/A converter and a voltage controlled oscillator generate a clock signal from the phase difference information to control the sampling timing of the A/D converter.

Abstract: In an information detecting circuit an equalizer equalizes an output from an A/D converter as an A/D converting information. A first interpolation circuit generates an interpolating value. A delay circuit delays the /VD converting information with a delay quantity equivalent to an output delay quantity of the equalizer. A second interpolation circuit generates an interpolating value. An interpolating position generating circuit produces an interpolating position information for generating an interpolating value synchronized in phase with the channel clock and supplies the interpolating position information into the first Interpolation circuit and the second interpolation circuit. A binary encoder converts the output of the first interpolation circuit. A tap coefficient controller generates a tap coefficient from interpolating value outputs of the first and second interpolations. A rate correcting circuit converts the tap coefficient to be fed-back to the equalizer.

Abstract: In a direct current fluctuation level detecting circuit, differences between sample values and a Viterbi detector reference level are summed in an interval of n samples using path selection information and minimum path metric information, which are detected in a Viterbi detector, and the function is completed through further operations in a branch difference generating circuit and an AS circuit. A direct current level V0 can be detected by a further process where an AS circuit output is multiplied by 1/n in a multiplier and the multiplication result is stored in a register. A timing generating circuit controls latching of the register and clearing of a path difference value with a cycle of n samples. A detected direct current level V0 is fed back to an input to compensate a direct current level fluctuation in an adaptive manner.

Abstract: In a PRML decoder, a branch metric calculator receives an input bit sequence having a multi-level multi-state characteristic precoded in a particular channel code and produces a set of branch metrics corresponding in number to amplitude levels which the input bit sequence assumes. ACS circuitry is formed of add/compare/select (ACS) circuits, adders and unit delay elements connected respectively to the ACS circuits and the adders.