Abstract: The invention provides a clock signal extraction circuit which can extract a synchronizing clock signal accurately from a readout waveform reproduced from information recorded in a high density and which includes substantial intersymbol interferences. An analog readout signal is converted into binary information with a synchronizing clock signal from a voltage controlled oscillator. A replica signal is produced from the binary information by a waveform replica production circuit while time corrected readout waveform data are produced from the analog readout signal by a delay circuit, and a phase amount is detected from the time corrected readout waveform data and the replica signal by a phase amount detection circuit. The base amount is used to control the voltage controlled oscillator, thereby forming a phase locked loop to perform a follow-up operation to the readout signal.

Abstract: An information detecting device comprises a multiplier for multiplying a gain g by a reproduced digital signal reproduced out of an optical recording medium to produce a multiplication result. A maximum likelihood detector is for use in carrying out, in response to the multiplication result, pulsing operation according to the multiplication result to produce a pulse string. A replica generator is for use in producing, in response to the pulse string, a replica waveform having an ideal channel property out of the pulse string. A delay circuit is for use in producing, in response to the reproduced digital signal, a delayed signal having the same phase as the replica waveform.

Abstract: A PRML (Partial Response Maximum Likelihood) signal processing apparatus for both MP (Mark Position) recorded medium and ME (Mark Edge) recorded medium. The apparatus has a PR (Partial Response) equalizer to which the reproduction signal from the medium is inputted, a folded back value calculation circuit for folding back an input signal thereto with a predetermined level, and a Viterbi detector having a path memory and performing a Viterbi detection. The path memory is constructed based on a structure of a trellis for a signal recorded by the MP recording. In case of the MP recorded medium, the equalizer transfer characteristics and the reference amplitude both for the MP recording are set to the PR equalizer and the Viterbi detector, respectively, and the output of the PR equalizer is directly supplied to the Viterbi detector.

Abstract: A level sensor circuit compares a threshold level from a threshold value generator circuit with that of an input sampling signal to create a binarized pulsated signal. A change point detector circuit detects a change point of binary information indicated by the input pulsates signal or positions before and after the change point and thereby sends a change point detection signal(s) to a threshold level generator circuit. The threshold level generator circuit extracts from the sampling signals only ones at points of time when the change point detection signal is inputted from the change point detector circuit and then averages the extracted sampling signals with respect to time to generate a threshold level.