Abstract: To provide a base station apparatus, a terminal apparatus, and a communication method capable of improving a frequency efficiency or throughput by suppressing an overhead associated with feedback from the terminal apparatus in a case that the base station apparatus acquires highly accurate CSI. A terminal apparatus according to an aspect of the present invention includes a receiver configured to receive at least one NZP CSI-RS, and a transmitter configured to transmit a signal including at least one piece of CSI. The at least one piece of CSI includes at least an RI and a PMI, the receiver acquires a first value for configuring the number of vectors indicated by the PMI, and in a case that a value of the RI exceeds a prescribed value, the number of vectors is configured by a second value being a value equal to or less than the first value.

Abstract: An object of the present invention is to propose a partial discharge determination device and method that can highly reliably determine the degree of progress of partial discharge occurring in an underground power transmission cable without preparing plural standard patterns. A distribution pattern of a set of the charge amount and the occurrence phase angle of each partial discharge occurring in a period of one or more cycles of an applied voltage of a power transmission cable is sequentially generated, a first classification process in which the pattern is classified into any one of classes on the basis of a standard distribution pattern for each class and a second classification process in which the distribution pattern are executed, a classification result by the first classification process is evaluated on the basis of a classification result by the second classification process, and the degree of progress is determined.

Abstract: An internal combustion engine exhaust purification device includes a filter which is disposed in an exhaust path and collects particulate matter in exhaust gas, an injection valve which is disposed upstream of the filter in the exhaust path and injects fuel into the exhaust path, a fuel pump which supplies a fuel to the injection valve, a shut-off valve which is interposed between the fuel pump and the injection valve, and selectively shuts off a fuel supply from the fuel pump to the injection valve, and a control unit which controls the injection valve and the shut-off valve. The control unit closes the shut-off valve when the control unit detects an opened adherence failure of the injection valve and detects an abnormal temperature rise of the filter during regeneration of the filter.

Abstract: A distribution pattern of a combination of a charge quantity and an occurrence phase angle of each of the partial discharges occurring in one or a plurality of cycle periods of an applied voltage of the power transmission cable is generated, differential data including a difference between the numbers of occurrences of the partial discharge for each combination of the charge quantity and the occurrence phase angle in two or more latest distribution patterns is generated, and the degree of progress of the partial discharge is determined based on data of the latest distribution patterns and the differential data.

Abstract: This fastening structure 100 on the exhaust side of an internal combustion engine 1 is provided with: a male threaded shaft 10; a pressing body 20 screwed or fixed to the male threaded shaft 10; a through-hole 30 which is formed in a fastening target component 3 and into which the male threaded shaft 10 is inserted; a threaded hole 40 which is formed in a component 2 to be fastened and into which the male threaded shaft 10 is screwed; and a tubular component 50 which is interposed between the pressing body 20 and the fastening target component 3 and into which the male threaded shaft 10 is inserted. The tubular component 50 has a linear expansion coefficient ?2 that is greater than the linear expansion coefficient ?1 of the fastening target component 3.

Abstract: An object of the present invention is to propose a partial discharge determination device and method that can highly reliably determine the degree of progress of partial discharge occurring in an underground power transmission cable without preparing plural standard patterns. A distribution pattern of a set of the charge amount and the occurrence phase angle of each partial discharge occurring in a period of one or more cycles of an applied voltage of a power transmission cable is sequentially generated, a first classification process in which the pattern is classified into any one of classes on the basis of a standard distribution pattern for each class and a second classification process in which the distribution pattern are executed, a classification result by the first classification process is evaluated on the basis of a classification result by the second classification process, and the degree of progress is determined.

Abstract: An internal combustion engine exhaust purification device includes a filter which is disposed in an exhaust path and collects particulate matter in exhaust gas, an injection valve which is disposed upstream of the filter in the exhaust path and injects fuel into the exhaust path, a fuel pump which supplies a fuel to the injection valve, a shut-off valve which is interposed between the fuel pump and the injection valve, and selectively shuts off a fuel supply from the fuel pump to the injection valve, and a control unit which controls the injection valve and the shut-off valve. The control unit closes the shut-off valve when the control unit detects an opened adherence failure of the injection valve and detects an abnormal temperature rise of the filter during regeneration of the filter.

Abstract: Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

Abstract: Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.

Abstract: Data on a memory space are compared without using a CPU, and an interrupt is generated in an interrupt condition based on at least one of the number of times of the comparison and the number of times of coincidence with a comparison condition. An interrupt controller outputs an interrupt signal to a first CPU core or a second CPU core. A DMAC transfers data on the memory space to at least one of a first buffer and a second buffer. A comparison circuit compares the data of the first buffer with the data of the second buffer. A condition coincidence frequency counter counts the number of times at which the comparison in the comparison circuit coincides with a comparison condition. An interrupt request circuit outputs an interrupt request to the interrupt controller, based on at least one of a value of the condition coincidence frequency counter and a value of a comparison frequency counter.

Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Abstract: Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication.

Abstract: Provided is an integrated circuit or the like capable of rapidly correcting erroneous data write and making contents of the RAMs that are in the multiple modular redundancy coincident in a case where a logic circuit performs the erroneous data write to the RAMs while operating logic circuits and RAMs at a high speed. In order to solve the problem, the integrated circuit including logic circuits and RAMs for which data write and data read are performed by the logic circuits includes a multiple modular redundancy logic circuits, a plurality of RAMs respectively connected to the multiple modular redundancy logic circuits, and a RAM access correction unit which compares access signals from the multiple modular redundancy logic circuit to the RAMs to detect an erroneous data write and corrects an error of the RAM.

Abstract: In a system for performing clock generation for each semiconductor device, synchronization between the semiconductor devices is achieved without causing a count value in a counter to be discontinuously changed.

Abstract: Provided are a communication processing device and a communication system, capable of securely updating a communication protocol process with a simple configuration and technique, while continuing communication.

Abstract: The present invention aims to provide a programmable device with a configuration memory that can hold the state of the occurrence abnormal situation that is difficult to assume such as a failure occurring in the programmable device due to the terrestrial radiation of the configuration memory, even during power off, in order to improve the reproducibility in device testing based on the held error information. The programmable device with the configuration memory includes: an error detection section for detecting an error in the configuration memory, and outputting the detected error as well as an address in which the error occurred, as error information; and an error information holding section provided with a non-volatile memory to store the output error information.

Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

Abstract: A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

Abstract: To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.