Abstract: This invention provides communications systems that enable broadcasting while making use of the simplicity of the prior art and also provides control devices and information processing systems incorporating the communications system. In this invention, chip-select signals are provided for transmitting (TXCSi) and receiving (RXCSi) independently as well as for individual chips as in the prior art. That is, a group of signals indicating whether or not a slave node is selected as the node to transmit signals to a master node and the direction of communications are output from the master node to the slave node.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A micro-controller includes a dictionary memory for storing instruction codes which appear in a program, and a compressed code memory for storing compressed codes each converted from each of the instruction codes included in the program. Each compressed code has a word length sufficiently long to identify all instruction codes included in the program. Each compressed code has a value indicative of an address in the dictionary memory at which an associated instruction code is stored. The micro-controller is responsive to an instruction code read request which specifies an address of a compressed code to read the compressed code stored in the specified address in the compressed code memory, and to subsequently read an instruction code stored in an address indicated by the compressed code in the dictionary memory.

Abstract: A master unit sends a start signal to a slave unit. When receiving the start signal from the master unit, the slave unit sends, to the master unit, a synchronization field that is a data train (pulse signal) indicative of a transfer clock with which the slave unit is able to perform transferring and receiving operations. The master unit sends, to the slave unit, command data in accordance with the transfer clock indicated by the synchronization field sent from the slave unit. In response to the command data sent from the master unit, the slave unit sends, to the master unit, response data in accordance with the transfer clock indicated by the synchronization field. Thus, in a communication system employing a serial data transferring apparatus of the present invention, the master unit establishes the synchronization for the data transfer, while the slave unit is free from a burden of establishing the synchronization for the data transfer.

Abstract: In an A/D converter and a microcontroller including the same, the number of selection patterns of analog input channels is increased for each A/D conversion and the A/D conversion is conducted using an A/D converter having only fundamental functions without imposing load onto a CPU. The A/D converter or a DMA transfer device includes an A/D conversion table including one or more entries. Each entry includes enable bits for setting whether or not an A/D conversion is executed for the respective analog input channels and a plurality of count number bits for setting a number of executions of the A/D conversion.

Abstract: The invention provides a code compression technology that is favorable for a micro controller or other embedded system, and for compressed codes, resulting from conversion of program codes into variable length codes, and grouped program codes, address conversion information for specifying the start address of each group and compressed code type information for specifying the code length of each compressed code contained in a group are stored in a memory, and by enabling a corresponding compressed code address to be calculated from a code address output by a CPU, code compression that is favorable for a micro controller or other embedded system is realized.

Abstract: A clamping apparatus includes upper and lower platens; one or more tiebars connecting the platens; and an intermediate platen between the upper and lower platens for movement relative to and along the tiebars. Upper and lower mold halves are provided on the upper and intermediate platens, respectively. A linkage connects the lower and intermediate platens. The linkage includes upper and lower links connected with each other for rotation on an intermediate shaft. The upper and lower links are pivotably supported on first and second shafts fixed to the intermediate and lower platens, repectively. The intermediate shaft is operatively connected with a drive mechanism so that the drive mechanism transmits a driving force to the linkage, and the lower platen is moved relative to the intermediate platen. A set of a radical needle bearing and a thrust bearing is used for at least one of the intermediate, first, and second shafts.

Abstract: A microprocessor for processing a large quantity of graphics data. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. A graphics processing apparatus provided by the microprocessor transfers graphics data between a system memory and a frame memory at high speeds.

Abstract: A water-in-oil (W/O) emulsion ink for stencil printing is provided which is prevented from pigment aggregation and thus excellent in ink fixability, high in printing density and less declining in printing density even after printing many sheets. The emulsion ink has a ratio by volume of the water phase to liquid components of the oil phase (i.e., volume of water phase/volume of the liquid components of oil phase) in a range of 1.0 to 3.5, preferably 1.0 to 3.0 at 23° C. The liquid components of the oil phase may be composed of a resin, a solvent and a surfactant. The oil phase can contain a pigment at a ratio by volume of 0.19 or less to the total volume of the oil phase. The pigment preferably has an average particle size of 0.02 to 1.5 (&mgr;m). The water phase preferably has an average particle size of 0.1 to 1.0 (&mgr;m). The ink is suitable for containing particles of organic pigments with non-uniform shapes and a large average particle size like copper phthalocyanine blue and diaxazine violet.

Abstract: The present invention prevents a data processor from undesirable operation stop due to an overflow of a plurality of register banks. A status register includes an overflow flag to indicate an overflow of the plurality of register banks. When an interrupt exception occurs in a state in which data has been saved to all banks of the register banks, and the accepted interrupt exception is permitted to use the register banks, a central processing unit saves data of a register set to a stack area and reflects an overflow state in the overflow flag. When the overflow flag indicates an overflow state, if data restoration from the register banks to the register set is directed, the central processing unit restores the data from the stack area to the register set.

Abstract: A data processor of the present invention efficiently performs decision processing on register conflict. The data processor contains n-bit instructions and 2n-bit instructions in an instruction set and includes an instruction control unit that can decide whether registers specified in register specification fields of the instructions conflict between the instructions. The 2n-bit instructions including register specification fields have the register specification fields in the first half n bits thereof, and the register specification fields in the first half n bits comprise the same placement as register specification fields in the n-bit instructions. Shift operations required to cut out the register specification fields from the instructions, either 2n-bit or n-bit instructions, can be simplified or deleted by aligning the register specification fields in the 2n-bit instructions with those in the n-bit instructions.

Abstract: A microprocessor suitable for processing a large quantity of graphics data. Graphics processing apparatus and method using the microprocessor are also disclosed. The microprocessor independent of a CPU has two ports, and performs an instruction fetch and a data access or a memory access simultaneously to two memories mounted on separate buses. In the graphics processing apparatus in which this microprocessor is employed, the graphics transfer between a system memory and a frame memory can be performed at higher speed.

Abstract: An oxide phosphor includes an oxide consisting of at least Gd, Ce, Al, Ga, and O, and has the crystal structure of a garnet structure, the atomic ratio (Gd+Ce)/(Al+Ga+Gd+Ce) of which is more than 0.375 and 0.44 or less, and the atomic ratio Ce/(Ce+Gd) of which is 0.0005 or more and 0.02 or less. This oxide phosphor reduces composition misalignment occurring during sintering, being a drawback of a phosphor having (Gd1-xCex)3Al5-yGayO12 composition, and has a property of extremely small afterglow and high luminescence efficiency. By using this oxide phosphor as a scintillator of a radiation detector having a light detector, the radiation detector with low afterglow and high output can be obtained. Further, by applying this radiation detector to an X-ray CT apparatus, a tomogram with high resolution and high quality can be obtained.

Abstract: A novel phosphor represented by the general formula (Gd1-y-zCeyScz)3Al5-dGadO12 (wherein y, z and d are values falling in the ranges of 0.0005≦y≦0.05, 0<z≦0.03 and 0<d<5) is provided by adding scandium (Sc) to a phosphor represented by the general formula of (Gd1-yCey)3Al5-dGadO12 (wherein y and d are values falling in the ranges of 0.0005≦y≦0.02 and 0<d<5). The phosphor has a high luminous efficiency and a very small afterglow. A radiation detector using this phosphor as ceramic scintillator is capable of obtaining a high luminous output and suitable for a radiation detector of X-ray CT because of its high luminous output and a very small afterglow.

Abstract: Green-emitting phosphor having a composition formula represented by (Y1-x-aGdxMa)3-3yTb3y(Al1-zGaz)5O12, where 0<x≦1, 0≦a<1, 0<x+a≦1, 0<y<1 and 0≦z≦1 and M is at least one of Sc, Yb and La, improves emission color of phosphors of Y3(Al, Ga)5O12:Tb series, and in case that y=0.07, z=0.4 and a=0 in the foregoing composition, color y is increased with increasing Gd concentration, when Gd concentration x is changed, and the emission color becomes clear green.

Abstract: A semiconductor integrated circuit device, responsive to an input signal having a low amplitude and short transition time, operates with low power consumption and prevents the flow of breakthrough current. In an example circuit thereof, the input signal is transmitted through an NMOS pass transistor to the gate of a first NMOS transistor and is applied, through a second NMOS transistor, to the gate of a first PMOS transistor, the first PMOS transistor performing complementary operation with the first NMOS transistor through the second NMOS transistor; the gate of the first PMOS transistor is connected to the power supply potential through the second PMOS transistor; the gate of the second NMOS transistor is connected to the power supply potential; and the gate of the second PMOS transistor is controlled by the signal at a common drain connection of the first NMOS and first PMOS transistors.

Abstract: In logical compound of inter-subblock paths, circuits including all inter-subblock paths are generated. Logical compound is conducted for the generated circuits to achieve logical compound of the inter-subblock paths. By treating inter-subblock paths as intra-subblock paths, no input/output delay restriction is required for the logical compound of inter-subblock paths. This makes it possible to fully use performance of the logical compound tool, and hence the inter-subblock paths can be optimized through one operation of the processing.

Abstract: A novel phosphor represented by the general formula

Abstract: There is disclosed a circuit apparatus which is highly tolerant to noises and operates at a higher speed than a conventional completely complementary static CMOS circuit. To achieve this, the circuit apparatus features a plurality of CMOS static logic circuits which are series-connected and potential setting circuitry which is connected to the output parts of these logic circuits and sets the outputs of the output parts to a low level in synchronization with a clock signal, thus propagating signals by operation of the NMOS circuit. In other words, a signal propagation delay occurs only when the N-type logic block conducts. Therefore, circuit operation is speeded up and &agr; particle noise and noises due to charge redistribution effect or leakage current can be prevented.