Abstract: A processor system, includes a first central processing unit (CPU) that executes a redundant instruction set; and a second CPU that executes the redundant instruction set, wherein before the second CPU executes a redundant instruction among the redundant instruction set, the first CPU is able to execute n (n is a predetermined integer number) redundant instructions among the redundant instruction set, and wherein when an exception occurs during execution of the redundant instruction set in the first CPU, the first CPU executes an instruction for the exception as a non-redundant instruction.

Abstract: The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.

Abstract: A micro controller with fault detection function is provided, in which duplex processing by a program is realized without complicating the program. Peripheral circuits are provided with registers and execute processing based on a command. A central processing unit executes twice processing by the same program that accesses the register. A duplex access control circuit is configured with a peripheral bus access unit, a buffer, and a comparator unit. The peripheral bus access unit controls the access to the register by the central processing unit in the first program execution. The buffer stores the access information to the register in the first program execution. The comparator unit compares the access information in the second program execution with the access information stored in the access information storage unit. In the case of disagreement, an error signal is outputted to the central processing unit.

Abstract: A system in an industrial plant which has a plurality of manual valves for controlling an amount of fluid flowing through pipes provided in an industrial plant of an embodiment includes: a measuring instrument sensor measuring a state of the plant so as to output a signal indicating measurement result; a transmitter wirelessly transmitting the measured signal; a receiver wirelessly receiving the transmitted signal; and a monitoring and controlling device collecting the received signal, in which the receivers are provided to the manual valves.

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.

Abstract: To have a problem of occurrence of the same failure in failure detection of a microcontroller. A microcontroller has a CPU and a data access control circuit. The data access control circuit performs two types of accesses: an individual access in which a data access of the CPU is performed for each thread, and a shared access in which a data access of the CPU is performed by executing two threads. The data access control circuit detects a failure of the CPU by making a comparison between the command and the address, respectively, in the shared access generated by executing the two threads.

Abstract: First data to be written which is output from a function module (2) is supplied to a built-in memory (3) and a first buffer memory (11), and second data to be written which is output from the function module (2) is supplied to the built-in memory (3) and a second buffer memory (12). The first and second FIFO memories (13, 14) select and store data items having a predetermined number of outputs from a plurality of first and second output data items which are sequentially output from the first and second buffer memories (11, 12), and do not select other data items. A comparator (15) compares the data items having the predetermined number of outputs which are selected and are output by the first and second FIFO memories (13, 14) with each other.

Abstract: A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Abstract: The present invention provides a semiconductor integrated circuit device realizing improved detection of a failure while suppressing deterioration in performance. In a semiconductor integrated circuit device executing a plurality of threads while switching them synchronously with clocks, registers used for executing the threads are provided for the respective threads. Programs independent of each other and the same program as the threads are executed while being switched. In the case of executing the same program by a plurality of threads, a comparison circuit for comparing results of execution using registers provided in correspondence with the threads is provided.

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.

Abstract: A microcontroller capable of improving processing performance as a whole by executing different programs by a plurality of CPUs and capable of detecting abnormality for safety-required processing by evaluating results of the same processing executed by the plurality of CPUs. A plurality of processing systems including CPUs and memories are provided, data output from the CPUs in each of the processing systems is separately compressed and stored by compressors for each of the CPUs, respectively. The compressed storage data is mutually compared by a comparator, and abnormality of processing can be detected when the comparison result indicates a mismatch. Even when the timings by which the same processing results are obtained are different when the plurality of CPUs asynchronously execute the same processing, the processing results of both of them can be easily compared with each other since compression is carried out by the compressors.

Abstract: A microcontroller includes a central processing unit, a PWM signal generation unit which generates a PWM signal according to a generation condition of a PWM signal set by the central processing unit, and a diagnostic unit which inputs the generated PWM signal therein and detects a pulse period and a pulse width, based on the input signal and which determines whether the detected pulse period and pulse width respectively coincide with a pulse period and a pulse width corresponding to the generation condition.

Abstract: A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

Abstract: A microcontroller in which respective CPUs execute different applications so as to improve processing performance, and the respective CPUs execute an application that requires safety and mutually compare the results thereof so as to enhance the reliability of write data is provided. The microcontroller has a plurality of processing systems made up of a first CPU, a second CPU, a first memory and a second memory, and for the instruction processing about specific processing set in advance, the write to peripheral modules which are not multiplexed is executed twice, and the write data of the first time and the second time are mutually collated.

Abstract: This method is an error correction method such that, when an error is detected in a CPU with pipeline structure, a content of a register file is restored by a delayed register file which holds an execute completion state of an [Instruction N] correctly executed before this error, and a rollback control that re-executes an instruction from the [Instruction N+1] which is the next instruction of the [Instruction N] is performed. The method collects a parity check result of arbitrary Flip-Flops existing inside the CPU, and detects an error. As a result, the content of the register file is restored into the instruction execute completion state preceding to the instruction range likely to malfunction by the error, and the instruction can be roll backed from the beginning of the instruction range likely having malfunctioned by the error.

Abstract: A computer system which shortens standby time of CPUs and improves CPU processing efficiency of a performance mode upon switching from the performance mode (parallel operation) to a safety mode (master/checker operation) is provided. In a computer system including: at least two CPUs; a programmable interrupt controller for interrupting the CPUs; and a comparator for mutually comparing outputs of the CPUs, switching between the performance mode of executing mutually different processes by the CPUs, respectively, to improve performance and the safety mode of executing mutually the same processes by the CPUs and collating results by the comparator to detect failure can be carried out; CPUs to be interrupted can be set for each interrupt factor; and whether the performance mode is to be executed or the safety mode is to be executed can be set for each interrupt factor.

Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.

Abstract: Two data processing units having the same function, one of which is used for a master and the other for comparison, are provided, control of a circuit unit is performed by the master, the master data processing unit and the circuit unit are operated in synchronization with a first clock signal, the second data processing unit is operated in synchronization with a second clock signal having the same cycle and different phase from the first clock signal, and processing results of both the data processing units are compared in a comparison circuit. Flip flops are disposed on a signal path from the circuit unit to the comparison data processing unit and on a signal path from the master data processing unit to the comparator, and both the first and second clock signals are used for latch clocks of the flip flops in accordance with input signals thereof.