Abstract: An apparatus for detecting an abnormality in polishing of an edge portion of a substrate is provided. The apparatus includes: a substrate holder configured to rotate the substrate; a pressing device configured to press a polishing tool against the edge portion of the substrate to polish the edge portion; a measuring device configured to measure a position of the polishing tool relative to a surface of the substrate; and a controller configured to determine an amount of polishing of the substrate from the position of the polishing tool, calculate a polishing rate from the amount of polishing of the substrate, and judge that an abnormality in polishing of the edge portion of the substrate has occurred if the polishing rate is out of a predetermined range.

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. One of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Abstract: A semiconductor storage device includes a global bit line extending in a horizontal direction, a select transistor provided on the global bit line and including a first terminal connected to the global bit line, a bit line provided on the select transistor, extending in a vertical direction, and connected to a second terminal of the select transistor, a plurality of word lines and insulating layers that are stacked alternately in a vertical direction, a first variable resistance layer between one of the plurality of word lines and a first side surface of the bit line, a plurality of dummy word lines and insulating layers that are stacked alternately in the vertical direction and disposed at the same level as the plurality of word lines, and a second variable resistance layer between the plurality of dummy word lines and a second side surface of the bit line.

Abstract: A semiconductor memory device includes memory cell arrays that include a plurality of memory cells. A first control circuit with control transistors of a first conductivity type is in a first region below the memory cell arrays. A second control circuit includes a first transistor of a first conductivity type connected in parallel to a second transistor of a second conductivity type. one of the first and second transistors is connected to an end of at least one control transistor. The second control circuit delivers a voltage to the plurality of control transistors. The first transistor is disposed in the first region. The second transistor is disposed in a second region adjacent to the first region. The second region is below a gap between adjacent memory cell arrays.

Abstract: A substrate processing apparatus for processing a substrate includes a setting device that sets a plurality of recipe items including operation conditions of the substrate processing apparatus and a recipe generating device that acquires a plurality of recipe models obtained by changing values of the plurality of recipe items and experimenting or simulating a processing result of the substrate and analyzes the plurality of recipe models to generate a recipe, the recipe generating device combining a part or all of the plurality of recipe models to generate the recipe such that a calculation value of a processing result of the substrate by the recipe satisfies a predetermined condition.

Abstract: A semiconductor storage device includes first and second wirings that are in a first layer above the substrate, extend along a first direction, and are adjacent to each other along a second direction, third and fourth wirings that are in a second layer above the first layer, extend along the second direction, and are adjacent to each other along the first direction, first and second memory cells on the first wiring, and a third memory cell on the second wiring. The first to third memory cells each include a variable resistance element and a switching element. The switching element of the first memory cell includes a gate coupled to the third wiring. The switching elements of the second and third memory cells each include a gate coupled to the fourth wiring. The variable resistance elements of the first to third memory cells are formed with equal distances from each other.

Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

Abstract: A method of detecting an abnormality in polishing of a substrate is provided. The method includes: rotating the substrate; pressing a polishing tool against an edge portion of the substrate to polish the edge portion; measuring a position of the polishing tool relative to a surface of the substrate; determining an amount of polishing of the substrate from the position of the polishing tool; calculating a polishing rate from the amount of polishing of the substrate; and judging that an abnormality in polishing of the edge portion of the substrate has occurred if the polishing rate is out of a predetermined range.

Abstract: Detection of an abnormality in polishing of a substrate is provided. A measuring device measures a position of the polishing tool relative to a surface of the substrate. A controller determines an amount of polishing of the substrate from the position of the polishing tool; calculates a polishing rate from the amount of polishing of the substrate; and judges that an abnormality in polishing of the edge portion of the substrate has occurred if the polishing rate is out of a predetermined range exceeds a predetermined threshold value.

Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

Abstract: Disclosed is a substrate transfer apparatus including: a pair of hands facing with each other; an opening/closing mechanism configured to move the pair of hands symmetrically in an opening/closing direction; a driving unit configured to transmit a power to the opening/closing mechanism; and a controller configured to control an operation of the driving unit. The opening/closing mechanism includes: a rotating body configured to rotate depending on a moving amount of the pair of hands in the opening/closing direction, and a sensor configured to detect a rotating amount of the rotating body. The controller controls an operation of the driving unit based on a signal from the sensor.

Abstract: According to one embodiment, a magnetoresistive memory device includes a substrate having a first surface which includes a first direction; and memory elements each having a switchable resistance. A first column of memory elements lined up along the first direction is different from an adjacent second column of memory elements lined up along the first direction at positions of memory elements in the first direction.

Abstract: While a vehicle is decelerating starting at a braking start time, start-off pre-shifting starts when speed falls to a predetermined speed. At a vehicle stoppage time, an idle stop permission flag is not set to on if start-off pre-shifting is incomplete, even if idle stop permission conditions have been met. The idle stop permission flag is set to on when start-off pre-shifting is completed, and an idle stop flag is set to on and the engine stopped when engine rotational speed falls below a set speed. The engine is restarted in response to braking being released, and the idle stop flag is set to off and the idle stop control ended when the engine rotational speed reaches or exceeds a set speed. The restarting of the engine causes an engine-driven oil pump to dispense oil to be used as a medium to manifest an automatic clutch command hydraulic pressure.

Abstract: A semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.

Abstract: Under a specified condition where a torque converter is kept in a lockup state to prolong the fuel-cutoff time, because of vehicle coasting with an accelerator opening APO=0, a downshift command is generated and then an automatic transmission causes a reengagement downshift by a drop in a release-side clutch hydraulic pressure Poff and a rise in an engagement-side clutch hydraulic pressure Pon. During the reengagement downshift, the engagement-side clutch hydraulic pressure Pon is reduced from a high lockup-ON hydraulic pressure to a low lockup-OFF hydraulic pressure after the time when the lockup is predicted to be released, thus preventing a torque drawing-in tendency of transmission output torque, which may occur at the time of the beginning of the inertia phase, from increasing, and also reducing in the width of a subsequent change in vehicle deceleration G, and consequently enhancing the shift quality.

Abstract: A method of detecting an abnormality in polishing of a substrate is provided. The method includes: rotating the substrate; pressing a polishing tool against an edge portion of the substrate to polish the edge portion; measuring a position of the polishing tool relative to a surface of the substrate; determining an amount of polishing of the substrate from the position of the polishing tool; calculating a polishing rate from the amount of polishing of the substrate; and judging that an abnormality in polishing of the edge portion of the substrate has occurred if the polishing rate is out of a predetermined range.

Abstract: According to one embodiment, a semiconductor storage device includes a cell array including resistance change elements formed above a semiconductor substrate; first cell transistors formed on the semiconductor substrate and provided in association with the resistance change elements; first gate electrodes included in the first cell transistor and extending in a first direction; a first bit lines electrically connected to the resistance change elements respectively and extending in a second direction perpendicular to the first direction; a second bit lines electrically connected to one end of a current path of the first cell transistors respectively and extending in the second direction; and first active areas in which the first cell transistors are formed, and which extend in a direction crossing the first direction at a first angle.

Abstract: A memory device according to an embodiment includes a first memory cell array; a second memory cell array; and a multiplexer arranged between the first memory cell array and the second memory cell array, the multiplexer controlling the first memory cell array and the second memory cell array.

Abstract: A resistance change type memory device according to an embodiment includes a plurality of memory elements; a first to a fourth bit lines connected to the plurality of memory elements, respectively; a first to a fourth transistors connected at their one ends to the first to the fourth bit lines, respectively; a fifth transistor connected at its one end to the other ends of the first and second transistors; a sixth transistor connected at its one end to the other ends of the third and fourth transistors; and a fifth bit line connected to the other ends of the fifth and sixth transistors.