Abstract: A compact and highly accurate A/D converter includes series-connected computation cells, the number of which is equal to the number for bits in an output signal. The first computation cell includes a first comparison unit for subtracting a reference current from a first input current to generate a first current, and a second comparison unit for subtracting a second input current from the reference current to generate a second current. The second computation cell includes first and second comparison units having the same configurations as those in the first computation cell. The computation cells of latter stages have the same configurations as the second computation cell. Current mirror circuits included in the first and second comparison units of each computation cell generate the first and second currents. Each computation cell outputs a current having an absolute value in accordance with one of the first and second currents.

Abstract: Provided is a digital-analog converter circuit that enables, for example, securing an improved accurate analog signal voltage and preventing increase in the circuit size. A first node of each individual unit is connected to a middle node of a one-order higher unit than a unit having that first node. A second node of the each individual unit is connected to one of the first and second nodes provided in the one-order higher unit than the unit having that second node, the one being on the side connected to a resister section set to an impedance value 2Z. A hierarchical structure can be formed in which an opponent connection point of the second node is selected by a hierarchy switch section, whereby the each individual unit is parallel connected to the resister section provided in the one-order higher unit and set to the impedance value 2Z.

Abstract: A current mode A/D converter for reducing current consumption while enhancing resolution. The A/D converter includes a V/I conversion circuit for sampling and converting an input voltage to a current, an I/V conversion circuit for converting the current supplied from the V/I conversion circuit to a comparison voltage, a comparator for comparing the current based on the comparison voltage and a reference current, and an encoder for generating a digital output signal based on the output signal of the comparator.

Abstract: A current mode A/D converter for reducing current consumption while enhancing resolution. The A/D converter includes a V/I conversion circuit for sampling and converting an input voltage to a current, an I/V conversion circuit for converting the current supplied from the V/I conversion circuit to a comparison voltage, a comparator for comparing the current based on the comparison voltage and a reference current, and an encoder for generating a digital output signal based on the output signal of the comparator.

Abstract: A D/A conversion circuit for performing D/A conversion at high speeds. The D/A conversion circuit includes a resistor string including a plurality of resistor elements connected between a low-potential power supply and a high-potential power supply. A plurality of first switch groups are connected to the connection nodes between the resistor elements for selectively outputting voltages at the connection nodes. The outputs of the switches of the first switch groups are connected in common to a corresponding one of the nodes. The plurality of nodes are connected to an output terminal of the D/A conversion circuit via a second switch group. Predetermined switches of the first switch groups are connected in parallel to third switches to apply voltages to the nodes.

Abstract: An in-cylinder injection, spark ignited internal combustion engine including a fuel injection valve spraying fuel substantially in a sector having a relatively small thickness and spreading substantially vertically to implement homogenous combustion and stratified combustion, ensures that for stratified combustion a large portion of the sprayed fuel is injected into a cavity and thus sufficiently vaporized and positioned as a combustible air fuel mixture in a vicinity of an ignition plug. A fuel injection valve is arranged at a perimeter of an upper portion of the cylinder and a piston has a top surface provided with a cavity biased in location to be farther from the fluid injection valve and having a wall opposite the fuel injection valve deviating toward the cylinder's substantial center the fuel sprayed for stratified combustion through the fuel injection valve into the cavity.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1–7. The comparators 1–7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1–OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: Provided is a digital-analog converter circuit that enables, for example, securing an improved accurate analog signal voltage and preventing increase in the circuit size. A first node of each individual unit is connected to a middle node of a one-order higher unit than a unit having that first node. A second node of the each individual unit is connected to one of the first and second nodes provided in the one-order higher unit than the unit having that second node, the one being on the side connected to a resister section set to an impedance value 2Z. A hierarchical structure can be formed in which an opponent connection point of the second node is selected by a hierarchy switch section, whereby the each individual unit is parallel connected to the resister section provided in the one-order higher unit and set to the impedance value 2Z.

Abstract: An in-cylinder injection, spark ignited internal combustion engine including a fuel injection valve spraying fuel substantially in a sector having a relatively small thickness and spreading substantially vertically to implement homogenous combustion and stratified combustion, ensures that for stratified combustion a large portion of the sprayed fuel is injected into a cavity and thus sufficiently vaporized and positioned as a combustible air fuel mixture in a vicinity of an ignition plug. A fuel injection valve is arranged at a perimeter of an upper portion of the cylinder and a piston has a top surface provided with a cavity biased in location to be farther from the fuel injection valve and having a wall opposite the fuel injection valve deviating toward the cylinder's substantial center the fuel sprayed for stratified combustion through the fuel injection valve into the cavity.

Abstract: The present invention provides pharmaceutical compositions which can achieve good state of glycemic control and correct postprandial hyperglycemia and early morning fasting hyperglycemia. The present pharmaceutical composition is for administration before meal to control blood glucose, which comprises 5 to 45 mg, as a single dose, of mitiglinide or a pharmaceutically acceptable salt thereof, or a hydrate thereof (for example, mitiglinide calcium salt hydrate). And said compositions are extremely useful for prevention or treatment of, for example, type II diabetes, because the frequency of adverse drug reactions such as hypoglycemic symptoms and gastrointestinal disorders is low.

Abstract: The present invention provides pharmaceutical compositions which can achieve good state of glycemic control and correct postprandial hyperglycemia and early morning fasting hyperglycemia. The present pharmaceutical composition is for administration before meal to prevent or inhibit the progression of diabetic complication, which comprises 5 to 45 mg, as a single dose, of mitiglinide or a pharmaceutically acceptable salt thereof, or a hydrate thereof (for example, mitiglinide calcium salt hydrate). And said compositions are extremely useful for prevention or inhibition of progression of, for example, diabetic microvascular complications and arteriosclerotic diseases, because the frequency of adverse drug reactions such as hypoglycemic symptoms and gastrointestinal disorders is low.

Abstract: A double-faced splicing tape of the present invention splices a first web used for forming a tobacco rod and a second web in a stand-by state to and has a plurality of perforations extending in a longitudinal direction of the webs. Furthermore, the present invention provides a feeding device for making the double-faced splicing tape hang toward a feeding position located in between a main delivery path of the first web and a sub-delivery path of the second web.

Abstract: A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capacitor. The limiting circuit is connected to the high potential power supply and the charge control circuit to limit the voltage provided to the capacitor from the high potential power supply before the charge control circuit stops providing the voltage of the high potential power supply to the capacitor.

Abstract: An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Abstract: A level shift circuit including a capacitor, a charge control circuit, and a limiting circuit. The charge control circuit is connected to the capacitor to provide the voltage of a high potential power supply to the capacitor and to control the charging of the capacitor. The limiting circuit is connected to the high potential power supply and the charge control circuit to limit the voltage provided to the capacitor from the high potential power supply before the charge control circuit stops providing the voltage of the high potential power supply to the capacitor.

Abstract: A piezoelectric element including a vibrating plate, a lower electrode, a piezoelectric film and an upper electrode laminated in this order, wherein the lower electrode, the upper electrode and the piezoelectric film are formed by a perovskite type oxide while the vibrating plate is formed by a metal oxide, and a junction interface is substantially absent between the vibrating plate and the lower electrode, between the lower electrode and the piezoelectric film and between the piezoelectric film and the upper electrode.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONTLA etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.

Abstract: A double-faced splicing tape of the present invention splices a first web used for forming a tobacco rod and a second web in a stand-by state to and has a plurality of perforations extending in a longitudinal direction of the webs. Furthermore, the present invention provides a feeding device for making the double-faced splicing tape hang toward a feeding position located in between a main delivery path of the first web and a sub-delivery path of the second web.

Abstract: An operational amplifier circuit includes a first differential pair, which includes first and second transistors, and a second differential pair, which includes third and fourth transistors. A fifth transistor is connected to the first and third transistors. A sixth transistor is connected to the second and fourth transistors. A first current source is connected to the first differential pair to provide a first bias current. A second current source is connected to the second differential pair to provide a second bias current. A third current source is connected to the fifth transistor to provide a third bias current. A fourth current source is connected to the sixth transistor provide a fourth bias current. A control circuit controls the first to fourth current sources such that the sum of the first and second bias currents is constant and the second to fourth bias currents become substantially equal.

Abstract: It is intended to provide an A/D converter circuit with which, by using a clock signal, on the basis of an analog voltage inputted a predetermined time past, it is possible to select suitably comparators to be operated and comparators to be rested, and which has small consumed power. A parallel-type A/D-converter circuit 200 converts an analog voltage VIN to a digital value DOUT at intervals of a predetermined period by means of a clock signal CLK using chopper-type comparators 1-7. The comparators 1-7 can each be set by first and second setting signals CONT1A etc. to either of an operating state and a resting state. A comparator control circuit section 211 performs logical processing on the comparator outputs OUT1-OUT7 in the preceding conversion to generate the first and second setting signals CONT1A etc., and brings some of the comparators to the operating state and holds the remaining comparators in the resting state.