Abstract: An object of the present invention is to provide a power module having high reliability. The power module according to the present invention, includes a circuit body and a case housing the circuit body. The case has a first case member including a first base plate and a second case member including a second base plate. The first case member has a first side wall portion formed in an arrangement direction of the first base plate and the second base plate. The second case member has a second side wall portion formed in the arrangement direction, the second side wall portion coupling to the first side wall portion. The first side wall portion and the second side wall portion are formed so as to have the sum of lengths of the first side wall portion and the second side wall portion in the arrangement direction smaller than the thickness of the circuit body. The first case member has a deforming portion smaller than the first base plate and the second base plate in rigidity.

Abstract: A power conversion apparatus includes: a circuit body including a switching device; a base member forming a first concave portion and a cooling surface; and a wedge inserted in the first concave portion of the base member. The first concave portion of the base member is formed by a substrate portion forming the cooling surface, a first wall disposed on the opposite side of the substrate portion from the cooling surface, and an intermediate portion interconnecting the first wall and the substrate portion. The first wall forms an insertion space for insertion of the wedge, and a heat transfer plane forming a heat dissipating surface and a heat transfer path of the circuit body. The intermediate portion is plastically deformed by inserting the wedge into the insertion space, thus causing the first wall to be displaced toward the location of the circuit body.

Abstract: In order to efficiently cool a heat-generating semiconductor element, it is desirable to cool a power semiconductor element from both surfaces. Therefore, in order to cool multiple power semiconductor elements, it is an effective way to alternately arrange a semiconductor component having the incorporated semiconductor element and a cooling device. A power conversion device for handling a high-power voltage needs to ensure pressure resistance between semiconductor elements or circuits inside the device. It is an effective way to seal the semiconductor component with a sealing material such as a silicone gel. Therefore, it is necessary to install the semiconductor component or the circuit having the incorporated semiconductor element, in a case from which a liquid silicone gel prior to curing does not leak even if the gel is injected.

Abstract: An object of the present invention is to provide a power module having high reliability. The power module according to the present invention, includes a circuit body and a case housing the circuit body. The case has a first case member including a first base plate and a second case member including a second base plate. The first case member has a first side wall portion formed in an arrangement direction of the first base plate and the second base plate. The second case member has a second side wall portion formed in the arrangement direction, the second side wall portion coupling to the first side wall portion. The first side wall portion and the second side wall portion are formed so as to have the sum of lengths of the first side wall portion and the second side wall portion in the arrangement direction smaller than the thickness of the circuit body. The first case member has a deforming portion smaller than the first base plate and the second base plate in rigidity.

Abstract: A power conversion apparatus includes: a circuit body including a switching device; a base member forming a first concave portion and a cooling surface; and a wedge inserted in the first concave portion of the base member. The first concave portion of the base member is formed by a substrate portion forming the cooling surface, a first wall disposed on the opposite side of the substrate portion from the cooling surface, and an intermediate portion interconnecting the first wall and the substrate portion. The first wall forms an insertion space for insertion of the wedge, and a heat transfer plane forming a heat dissipating surface and a heat transfer path of the circuit body. The intermediate portion is plastically deformed by inserting the wedge into the insertion space, thus causing the first wall to be displaced toward the location of the circuit body.

Abstract: A power module or the like is provided in which lower inductance and miniaturization are achieved. The power module includes: main body units (11 to 13), cooling units (21 to 24) which cool the main body units (11 to 13), busbars (51, 52) connected to power terminals (1i, 1j) of the main body units (11 to 13), a casing (W) in which at least contact parts with the busbars (51, 52) are insulative, and a metal member (30) which supports the casing (W). The metal member (30) tightly contacts the casing (W), thereby forming a box with one side opened. At least the main body units (11 to 13) and the busbars (51, 52) are arranged inside the box. An insulating sealant is provided to fill the inside of the box.

Abstract: Provided are a method and an apparatus for producing nanostructures. The method and the apparatus can form the nanostructures having fine dimensions from a wider variety of materials. Also provided is a substrate structure including nanostructures formed from a material that is industrially widely applicable. A method forms a plurality of nanostructures on a flat surface of a substrate. The method includes the step a) of evaporating a main material for the nanostructures onto the flat surface of the substrate. In the step a), the substrate is controlled to have an absolute temperature equal to or lower than 0.25 time the melting point (absolute temperature) of the main material for the nanostructures. This enables the formation of fine nanostructures having a desired shape from a desired material.

Abstract: In order to achieve both a reduction in thermal resistance and an improvement in thermal deformation absorbing property of a semiconductor device having a packaging structure in which a semiconductor chip 1 is electrically connected to conductive members 3a and 3b via bonding members 2a and 2b, the bonding members 2a and 2b each includes a stacked structure provided with, in the order from the side close to the semiconductor chip 1, a nanospring layer 4 configured from a plurality of springs having a nano-order size, a planar layer 5 supporting the plurality of springs, and a bonding layer 6. The thickness of the nanospring layer 4 is larger than the thickness of the bonding layer 6, and the thickness of the bonding layer 6 is larger than the thickness of the planar layer 5.

Abstract: The purpose of the present invention is to provide a power semiconductor device which has a light weight, high heat dissipation efficiency, and high rigidity. The power semiconductor device including a base 1, semiconductor circuits 2 which are arranged on the base 1, and a cooling fin 3 which cools each of the semiconductor circuits 2, in which one or more protruding portions 1a, 1b are formed on the base 1, widths of the protruding portions 1a, 1b in a direction parallel to the base 1 surface being longer than a thickness of the base 1, thereby providing power semiconductor devices 100, 200, 300, 400 which have a light weight, high heat dissipation efficiency, and high rigidity.

Abstract: A semiconductor device has a packaging structure in which a top surface of a semiconductor chip 1 is electrically connected to a conductive member 4 through a deformation absorption layer 2a and a joining layer 3a and a bottom surface thereof is electrically connected to a conductive member 5 through a deformation absorption layer 2b and a joining layer 3b. Each of the deformation absorption layers 2a and 2b includes a nano-structure layer 7 arranged at a center of a thickness direction and plate layers 6 and 8 of two layers with the nano-structure layer 7 therebetween. The nano-structure layer 7 has a structure in which a plurality of nano-structures 9 having a size of 1 ?m or less are two-dimensionally arranged and thermal stress due to a thermal deformation difference of each member forming the semiconductor device is absorbed by deformation of the nano-structures 9.

Abstract: Disclosed herein is a device that includes: a semiconductor substrate having a first surface on which a plurality of circuit elements are formed and a second surface opposite to the first surface; an insulating layer covering the second surface of the semiconductor substrate; and a penetration electrode having a body section that penetrates through the semiconductor substrate and a protruding section that is connected to one end of the body section and protrudes from the second surface of the semiconductor substrate. The second surface of the semiconductor substrate is covered with the protruding section of the penetration electrode without intervention of the insulating layer.

Abstract: A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.

Abstract: A life prediction method of an electronic device in which the life prediction accuracy is more improved than that in a related art technique, and a design method of an electronic device based on the above method, are established. Life prediction is performed by incorporating either of a change in a physical property of a solder joint portion and a change in the fatigue life of a solder, the changes occurring when left at a high temperature. The change in a physical property of the solder joint portion or the change in the fatigue life of the solder is determined from the relationship between a heat treatment temperature and a heat treatment time. These changes are then formulated to be incorporated into the life prediction.

Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.

Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.

Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.

Abstract: A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.