Patents by Inventor Hisashi Tanie

Hisashi Tanie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060249829
    Abstract: A stacked type semiconductor device comprising: a baseboard having a terminal row formed at an end in which connecting terminals is arranged linearly and having a wiring pattern connected to the connecting terminals and external terminals; semiconductor chips having a pad row in which pads is arranged linearly in parallel to the terminal row and being stacked on the baseboard; and interposer boards having a wiring layer including a plurality of wires arranged in parallel with the same length for connecting between pads of the pad row and connecting terminals of the terminal row.
    Type: Application
    Filed: April 7, 2006
    Publication date: November 9, 2006
    Inventors: Mitsuaki Katagiri, Masanori Shibamoto, Tsutomu Hara, Koichiro Aoki, Naoya Kanda, Shuji Kikuchi, Hisashi Tanie
  • Patent number: 7119428
    Abstract: A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: October 10, 2006
    Assignees: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Hisashi Tanie, Nae Hisano, Hiroyuki Ohta, Hiroaki Ikeda, Ichiro Anjo, Mitsuaki Katagiri, Yuji Watanabe
  • Publication number: 20060216848
    Abstract: A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.
    Type: Application
    Filed: February 9, 2006
    Publication date: September 28, 2006
    Inventors: Hisashi Tanie, Takashi Sumigawa, Hiroyuki Ohta
  • Publication number: 20050236697
    Abstract: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.
    Type: Application
    Filed: February 24, 2005
    Publication date: October 27, 2005
    Inventors: Mitsuaki Katagiri, Hisashi Tanie
  • Publication number: 20050230824
    Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.
    Type: Application
    Filed: April 14, 2005
    Publication date: October 20, 2005
    Inventors: Yuji Watanabe, Hisashi Tanie, Koji Hosokawa, Mitsuaki Katagiri, Ichiro Anjo
  • Publication number: 20050230829
    Abstract: A semiconductor device is provided with a semiconductor package 2 and a package substrate 5 having lands 8 that electrically connect by way of solder bumps 4 to the semiconductor package 2. A plurality of columns, in each of which a multiplicity of lands 8 are arranged, are formed on the package substrate 5. At least one of the lands 8 that make up columns that are located closest to each of the main sides that make up the outer edges of the semiconductor package has an interconnection 9 that extends from the land 8 along the surface of the package substrate. The interconnection 9 is formed such that the part that contacts the land 8 is located closer to a line that passes through the center of the land 8 and that is orthogonal to a line that connects the center of the land 8 with the center of the semiconductor package 2 than to the line that connects the center of the land 8 with the center of the semiconductor package 2.
    Type: Application
    Filed: March 17, 2005
    Publication date: October 20, 2005
    Inventors: Yuji Watanabe, Mitsuaki Katagiri, Hisashi Tanie, Atsushi Nakamura, Tomohiko Sato
  • Publication number: 20050212104
    Abstract: By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which said mount board is supported through a connection member, wherein the connection member consists of a first mount board connection portion with the mount board at a first side of the element in a direction along a main surface of the mount board in which the semiconductor element is mounted, and consists of a first support member connection portion with the support member at a second side in opposition to the first side through the semiconductor element.
    Type: Application
    Filed: January 25, 2005
    Publication date: September 29, 2005
    Applicant: Hitachi, Ltd.
    Inventor: Hisashi Tanie
  • Publication number: 20050189639
    Abstract: A semiconductor device capable of reducing a temperature increase during operation thereof is provided. In the semiconductor device, an interface chip is stacked on a plurality of stacked semiconductor elements. Both an “Si” interposer and a resin interposer are arranged under the plural semiconductor elements. The Si interposer is arranged between the resin interposer and the plural semiconductor elements. The Si interposer owns a thickness which is thicker than a thickness of a semiconductor element, and also has a linear expansion coefficient which is smaller than a linear expansion coefficient of the resin interposer, and further, is larger than, or equal to linear expansion coefficients of the plural semiconductor elements.
    Type: Application
    Filed: December 28, 2004
    Publication date: September 1, 2005
    Applicants: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Hisashi Tanie, Nae Hisano, Hiroyuki Ohta, Hiroaki Ikeda, Ichiro Anjoh, Mitsuaki Katagiri, Yuji Watanabe
  • Publication number: 20050001302
    Abstract: A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.
    Type: Application
    Filed: April 29, 2004
    Publication date: January 6, 2005
    Applicants: Hitachi, Ltd., Elpida Memory, Inc.
    Inventors: Hisashi Tanie, Nae Hisano, Koji Hosokawa