Patents by Inventor Hisashi Tanie
Hisashi Tanie has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7960846Abstract: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastomer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastomer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastomer by a length no smaller than the thickness of the elastomer.Type: GrantFiled: January 30, 2009Date of Patent: June 14, 2011Assignee: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Hisashi Tanie
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Publication number: 20100295162Abstract: Portions of a wiring layer extending like cantilevers from an inner peripheral edge of an opening in a substrate are joined to respective terminals of a semiconductor chip mounted on the substrate. A junction portion between each portion of the wiring layer and the corresponding terminal is sealed with resin.Type: ApplicationFiled: May 6, 2010Publication date: November 25, 2010Applicant: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Hisashi Tanie, Dai Sasaki
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Publication number: 20100295179Abstract: A BGA semiconductor device includes a semiconductor package and a mounting board mounting thereon the semiconductor package, wherein an array of signal electrodes of the semiconductor package and an array of signal electrodes of the mounting board are coupled together via signal bumps. The BGA semiconductor device also includes a dummy bump, which reinforces the bending strength of the BGA semiconductor device and is broken by a shearing force caused by thermal expansion to alleviate the stress for the signal bumps.Type: ApplicationFiled: July 29, 2010Publication date: November 25, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Yuji Watanabe, Hisashi Tanie, Koji Hosokawa, Mitsuaki Katagiri, Ichiro Anjo
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Publication number: 20100224984Abstract: A semiconductor device according to one embodiment has a wiring circuit board, a semiconductor chip, a die attach material and bumps. The semiconductor chip is mounted on the wiring circuit board. The die attach material is provided between the wiring circuit board and the semiconductor chip. A wiring layer is provided on one surface of the wiring circuit board. Leads are extended from the wiring layer and connected to the semiconductor chip. The bumps are provided at outer positions relative to the region where the semiconductor chip of the wiring circuit board is mounted. The wiring layer in the wiring circuit board is formed on the surface opposite from the surface on which the semiconductor chip is mounted.Type: ApplicationFiled: December 18, 2009Publication date: September 9, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Dai SASAKI, Mitsuaki KATAGIRI, Hisashi TANIE
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Publication number: 20100193936Abstract: A novel structure capable of reducing the stress in the insulating layer in the semiconductor element and thereby securing reliability is provided. When the semiconductor element and the substrate are connected with a solder, the stress generated in the insulating layer is reduced by placing a spherical core made of a material having a greater rigidity inside the solder and satisfying the following inequalities: 1 GPa<(Young's modulus of a encapsulation resin)<30 GPa, 20 ppm/k<(linear coefficient of expansion of the encapsulation resin)<200 ppm/k, and 10 MPa<(yield stress of the solder at room temperature)<30 MPa. At the time of connection, the thickness of the solder to be placed between the land on the surface of the semiconductor element and the core is adjusted to 1/10 or less of the terminal pitch.Type: ApplicationFiled: January 27, 2010Publication date: August 5, 2010Inventors: Hisashi TANIE, Nobuhiko Chiwata, Motoki Wakano, Takeyuki Itabashi
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Publication number: 20100171209Abstract: A semiconductor device having stacked semiconductor chips is provided wherein alignment of even thin semiconductor chips of a large warpage is easy and thus high assembling accuracy and high reliability are ensured. Semiconductor chips having hollow through-silicon via electrodes each formed with a tapered portion are melt-joined using solder balls each having a core of a material higher in melting point than solder. When melt-joining the semiconductor chips, the temperature is raised while imparting an urging load to stacked semiconductor chips, thereby correcting warpage of the semiconductor chips. In each chip-to-chip connection thus formed, if the connection is to prevent the occurrence of stress around the electrode due to the urging load, a solder ball having a core of a smaller diameter than in the other connections is used in the connection.Type: ApplicationFiled: January 5, 2010Publication date: July 8, 2010Inventors: Hisashi Tanie, Takeyuki Itabashi, Nobuhiko Chiwata, Motoki Wakano
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Patent number: 7714425Abstract: A semiconductor device includes a second semiconductor package, which includes a substrate and at least one semiconductor package. The substrate includes a terminal group formed on a surface thereof. At least one first semiconductor package is stacked on the substrate, and includes a plurality of flexible substrates, each of which includes a wiring group on a surface thereof and each of which is bending-deformable. At least one first semiconductor package includes a plurality of semiconductor elements mounted on a plurality of flexible substrates. Electric conduction through the second semiconductor package is established by connecting the wiring group on each of a plurality of flexible substrates to the terminal group on the substrate.Type: GrantFiled: September 19, 2008Date of Patent: May 11, 2010Assignee: Elpida Memory, Inc.Inventors: Masahiro Yamaguchi, Hisashi Tanie, Naoto Saito
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Publication number: 20100052133Abstract: A semiconductor device includes a plurality of semiconductor packages each with a semiconductor element and a flexible board. The flexible board is wider than the semiconductor element and is electrically connected to the semiconductor element. The plurality of semiconductor packages are stacked on one surface of a mother board. The semiconductor element is positioned between the flexible boards of the semiconductor packages in adjacent layers. The flexible boards in the adjacent layers are joined together at junction portions positioned at a part of the flexible boards which sticks out from an area in which the semiconductor elements and the flexible boards overlap. A reinforcing resin is provided in at least a part of the area between the flexible boards in the adjacent layers and between the junction portion of the flexible boards and the corresponding semiconductor element. The reinforcing resin contacts at least a part of the adjacent flexible board.Type: ApplicationFiled: July 1, 2009Publication date: March 4, 2010Applicant: Elpida Memory, Inc.Inventors: Hisashi TANIE, Hiroshi Moriya, Masahiro Yamaguchi, Emi Sawayama
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Publication number: 20100038767Abstract: The semiconductor device includes a stacked semiconductor package in which end portions of a plurality of flexible substrates have bonded portions which are connected together by wirings and in which a plurality of semiconductor packages are electrically connected to a mother substrate via the bonded portions. In at least a part of a region of portions of the plurality of flexible substrates that extends from the side surfaces of each of the semiconductor elements, and that is present between side surfaces of each of the semiconductor elements and the bonded portions of the flexible substrates, the plurality of flexible substrates have a curved portion, and the shape of the curved portion of at least one flexible substrate is different from the shape of a curved portion of another flexible substrate adjacent to this flexible substrate.Type: ApplicationFiled: August 10, 2009Publication date: February 18, 2010Applicant: ELPIDA MEMORY, INC.Inventors: Hiroshi MORIYA, Hisashi TANIE, Emi SAWAYAMA, Masahiro YAMAGUCHI
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Patent number: 7659623Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.Type: GrantFiled: April 7, 2006Date of Patent: February 9, 2010Assignee: Elpida Memory, Inc.Inventors: Yuji Watanabe, Koji Hosokawa, Hisashi Tanie
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Patent number: 7573128Abstract: A semiconductor module comprises: semiconductor packages each comprising a semiconductor element, a wiring substrate having a wiring member connected to the semiconductor element and external terminals connected to the wiring member, and a first organic film formed on a side of the semiconductor element opposed to a side toward the wiring substrate; and a mount substrate, on which the semiconductor element is mounted. First of the semiconductor packages and second of the semiconductor packages are stacked. Second organic films are provided between the wiring substrate of the first semiconductor package and the first organic film of the second semiconductor package and between the mount substrate and the semiconductor package.Type: GrantFiled: April 29, 2004Date of Patent: August 11, 2009Assignee: Hitachi, Ltd.Inventors: Hisashi Tanie, Nae Hisano, Koji Hosokawa
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Publication number: 20090184409Abstract: In a stacked-type semiconductor device, a first semiconductor device and at least one second semiconductor device are stacked. The first semiconductor device includes a wiring board and a first semiconductor chip mounted on the wiring board. The second semiconductor device includes a wiring board and a second semiconductor chip mounted on the wiring board. The thickness of the second semiconductor chip of each second semiconductor device is thicker than the thickness of the first semiconductor chip.Type: ApplicationFiled: January 22, 2009Publication date: July 23, 2009Applicant: Elpida Memory, Inc.Inventors: Mitsuaki KATAGIRI, Hisashi Tanie, Jun Kayamori, Dai Sasaki, Hiroshi Moriya
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Publication number: 20090140412Abstract: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.Type: ApplicationFiled: January 30, 2009Publication date: June 4, 2009Applicant: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Hisashi Tanie
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Publication number: 20090134506Abstract: A semiconductor device includes a second semiconductor package, which includes a substrate and at least one semiconductor package. The substrate includes a terminal group formed on a surface thereof. At least one first semiconductor package is stacked on the substrate, and includes a plurality of flexible substrates, each of which includes a wiring group on a surface thereof and each of which is bending-deformable. At least one first semiconductor package includes a plurality of semiconductor elements mounted on a plurality of flexible substrates. Electric conduction through the second semiconductor package is established by connecting the wiring group on each of a plurality of flexible substrates to the terminal group on the substrate.Type: ApplicationFiled: September 19, 2008Publication date: May 28, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Masahiro YAMAGUCHI, Hisashi Tanie, Naoto Saito
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Publication number: 20090134498Abstract: The present invention includes a semiconductor element provided with an electrode passing through front and back sides. The electrode is formed as a cylinder including a hollow portion, and stress relaxing material is provided in the hollow portion, which is used to reduce stress that is induced between the semiconductor element and the electrode. The stress relaxing material is an elastic body made of resin material.Type: ApplicationFiled: November 19, 2008Publication date: May 28, 2009Applicant: ELPIDA MEMORY, INC.Inventors: Hiroaki IKEDA, Masakazu Ishino, Hideharu Miyake, Shiro Uchiyama, Yasuhiro Naka, Nae Hisano, Hisashi Tanie, Kunihiko Nishi, Hiroyuki Tenmei
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Patent number: 7518202Abstract: A semiconductor mechanical quantity measuring apparatus in which the reverse surface of a strain-detecting semiconductor element is bonded to an object of measurement, and a member having a small elastic modulus is interposed between the wiring board for supporting the strain-detecting semiconductor element and the strain-detecting semiconductor element. It then becomes possible to reduce an undesirable effect that the rigidity and thermal deformation of the wiring board have on the strain-detecting semiconductor element, while supporting the strain-detecting semiconductor element.Type: GrantFiled: February 9, 2006Date of Patent: April 14, 2009Assignee: Hitachi, Ltd.Inventors: Hisashi Tanie, Takashi Sumigawa, Hiroyuki Ohta
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Patent number: 7504734Abstract: A semiconductor chip is mounted on a flexible wiring board through the interposition of an elastmer. The flexible wiring board is made up of a tape on which wiring is fixed. A part of the wiring is projected beyond the edge of the tape, extended in the direction of the thickness of the elastmer and connected to an electrode of the semiconductor chip. The edge of the tape beyond which the wiring is projected protrudes beyond the edge of the elastmer by a length no smaller than the thickness of the elastmer.Type: GrantFiled: February 24, 2005Date of Patent: March 17, 2009Assignee: Elpida Memory, Inc.Inventors: Mitsuaki Katagiri, Hisashi Tanie
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Publication number: 20080150115Abstract: An electronic component such as a semiconductor device is provided which is capable of preventing wiring breakage in a stress concentration region of surface layer wiring lines. In a semiconductor device provided with a support ball (5), no ordinary wiring line is formed in a region (7(A)) in the vicinity of the support ball (5) and a region (7(B)) at the end of the semiconductor chip facing the support ball (5), which are the stress concentration regions of the package substrate (2). Instead, a wiring line (6(C)) is formed away from these regions or a wide wiring line is formed in these regions.Type: ApplicationFiled: April 7, 2006Publication date: June 26, 2008Applicant: ELPIDA MEMORY INC.Inventors: Yuji Watanabe, Koji Hosokawa, Hisashi Tanie
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Patent number: 7239010Abstract: By securing a fatigue life of a connection portion with a semiconductor package and a mount board, a semiconductor device having a high reliability is provided. The semiconductor device consists of a semiconductor element, a mount board in which said semiconductor element is mounted, and a support member in which said mount board is supported through a connection member, wherein the connection member consists of a first mount board connection portion with the mount board at a first side of the element in a direction along a main surface of the mount board in which the semiconductor element is mounted, and consists of a first support member connection portion with the support member at a second side in opposition to the first side through the semiconductor element.Type: GrantFiled: January 25, 2005Date of Patent: July 3, 2007Assignee: Hitachi, Ltd.Inventor: Hisashi Tanie
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Publication number: 20070126095Abstract: A semiconductor device has a semiconductor package with a semiconductor element is mounted on a mounting substrate. The mounting substrate has at least two anisotropic areas which are located at both sides of a semiconductor package mounting area in a way to sandwich it and have an anisotropic linear expansion coefficient. In the anisotropic areas, a linear expansion coefficient in a direction toward a center of the semiconductor package mounting area is larger than a linear expansion coefficient in an in-plane direction of the mounting substrate perpendicular to the direction and larger than a linear expansion coefficient of the semiconductor package mounting area in a direction toward the anisotropic areas. The semiconductor device makes it possible to reduce thermal deformation of a semiconductor package mounting area of a mounting substrate easily and at low cost.Type: ApplicationFiled: November 30, 2006Publication date: June 7, 2007Applicant: Hitachi, Ltd.Inventor: Hisashi Tanie