Patents by Inventor Ho-Hsiang Chen

Ho-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210234508
    Abstract: In some embodiments, a differential oscillator includes a differential circuit coupled between a first output node and a second output node and a transformer-coupled band-pass filter (BPF). The transformer-coupled BPF is coupled between the first output node and the second output node and includes a coupling device and a transformer. The coupling device is coupled between the first output node and the second output node. The transformer includes a first winding coupled between the first output node and a voltage node and a second winding coupled between the second output node and the voltage node.
    Type: Application
    Filed: April 15, 2021
    Publication date: July 29, 2021
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20210184036
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: February 24, 2021
    Publication date: June 17, 2021
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Publication number: 20210167728
    Abstract: A band-pass filter (BPF) includes a pair of coupled transformers including first through fourth conductive structures. The first conductive structure includes a first terminal and two first extending portions extending from the first terminal and configured as primary windings. The second conductive structure includes a second terminal and two second extending portions extending from the second terminal. A first via connects the third conductive structure to a first one of the two second extending portions, the third conductive structure and the first one of the two second extending portions thereby being configured as a first secondary winding. A second via connects the fourth conductive structure to a second one of the two second extending portions, the fourth conductive structure and the second one of the two second extending portions thereby being configured as a second secondary winding.
    Type: Application
    Filed: February 11, 2021
    Publication date: June 3, 2021
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Patent number: 11023647
    Abstract: A method of verifying an integrated circuit stack includes adding a dummy layer to a contact pad of a functional circuit, wherein a location of the dummy layer is determined based on a location of a contact pad of a connecting substrate. The method further includes converting the dummy layer location to the connecting substrate. The method further includes determining whether the dummy layer is aligned with the contact pad of the connecting substrate. The method further includes adjusting the dummy layer location in the functional circuit when the dummy layer location is misaligned with the contact pad of the connecting substrate.
    Type: Grant
    Filed: March 14, 2018
    Date of Patent: June 1, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Feng Wei Kuo, Shuo-Mao Chen, Chin-Yuan Huang, Kai-Yun Lin, Ho-Hsiang Chen, Chewn-Pu Jou
  • Patent number: 10971296
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: April 28, 2020
    Date of Patent: April 6, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10964814
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: April 16, 2019
    Date of Patent: March 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Patent number: 10931230
    Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a pair of transistors. The pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.
    Type: Grant
    Filed: June 5, 2019
    Date of Patent: February 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.
    Inventors: Chi-Hsien Lin, Ho-Hsiang Chen, Hsien-Yuan Liao, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20200258672
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Application
    Filed: April 28, 2020
    Publication date: August 13, 2020
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Publication number: 20200227572
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: March 30, 2020
    Publication date: July 16, 2020
    Inventors: Hsiao-Tsung YEN, YU-LING LIN, CHIN-WEI KUO, HO-HSIANG CHEN, CHEWN-PU JOU, MIN-CHIE JENG
  • Patent number: 10665380
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: April 2, 2019
    Date of Patent: May 26, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10629756
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Grant
    Filed: March 15, 2018
    Date of Patent: April 21, 2020
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Chewn-Pu Jou, Min-Chie Jeng
  • Publication number: 20200004920
    Abstract: A phase shifter includes an active region, a first and a second set of gates and a set of contacts. The active region extends in a first direction and is located at a first level. The first and second set of gates each extend in a second direction, overlap the active region and are located at a second level. The second set of gates are positioned along opposite edges of the active region, are configured to receive a first voltage, and are part of a first transistor. The first transistor is configured to adjust a first capacitance of the phase shifter responsive to the first voltage. The set of contacts extend in the second direction, are over the active region, are located at a third level, and are positioned between at least the second set of gates.
    Type: Application
    Filed: June 14, 2019
    Publication date: January 2, 2020
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20200007080
    Abstract: A voltage-controlled oscillator (VCO) includes a power supply node configured to have a power supply voltage. A reference node is configured to have a first reference voltage. A transformer-coupled band-pass filter (BPF) is coupled to a cross-coupled pair of transistors. The cross-coupled pair of transistors and the transformer-coupled band-pass filter are positioned between the power supply node and the reference node.
    Type: Application
    Filed: June 5, 2019
    Publication date: January 2, 2020
    Inventors: Chi-Hsien LIN, Ho-Hsiang CHEN, Hsien-Yuan LIAO, Tzu-Jin YEH, Ying-Ta LU
  • Publication number: 20190245084
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Application
    Filed: April 16, 2019
    Publication date: August 8, 2019
    Inventors: HSIEN-YUAN LIAO, CHIEN-CHIH HO, CHI-HSIEN LIN, HUA-CHOU TSENG, HO-HSIANG CHEN, RU-GUN LIU, TZU-JIN YEH, YING-TA LU
  • Publication number: 20190228898
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Application
    Filed: April 2, 2019
    Publication date: July 25, 2019
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10276295
    Abstract: A device includes a substrate, and a vertical inductor over the substrate. The vertical inductor includes a plurality of parts formed of metal, wherein each of the parts extends in one of a plurality of planes perpendicular to a major surface of the substrate. Metal lines interconnect neighboring ones of the plurality of parts of the vertical inductor.
    Type: Grant
    Filed: January 30, 2017
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Hsiao-Tsung Yen, Huan-Neng Chen, Yu-Ling Lin, Chin-Wei Kuo, Mei-Show Chen, Ho-Hsiang Chen, Min-Chie Jeng
  • Patent number: 10276716
    Abstract: Semiconductor structures and methods for forming a semiconductor structure are provided. An active semiconductor region is disposed in a substrate. A gate is formed over the substrate. Source and drain regions of a transistor are formed in the active semiconductor region on opposite sides of the gate. The drain region has a first width, and the source region has a second width that is not equal to the first width.
    Type: Grant
    Filed: November 2, 2016
    Date of Patent: April 30, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Hsien-Yuan Liao, Chien-Chih Ho, Chi-Hsien Lin, Hua-Chou Tseng, Ho-Hsiang Chen, Ru-Gun Liu, Tzu-Jin Yeh, Ying-Ta Lu
  • Publication number: 20190103354
    Abstract: An integrated circuit includes an inductor over a substrate and a guard ring surrounding the inductor. The guard ring includes a first staggered line, a first metal line extending in a first direction and a second metal line extending in a second direction different from the first direction. The first staggered line has a first end coupled to the first metal line, and a second end coupled to the second metal line. The first staggered line includes a first set of vias, a first set of metal lines in a first metal layer and a second set of metal lines in a second metal layer different from the first metal layer. The first set of vias coupling the first set of metal lines with the second of second metal lines.
    Type: Application
    Filed: November 30, 2018
    Publication date: April 4, 2019
    Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
  • Patent number: 10163779
    Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.
    Type: Grant
    Filed: June 12, 2014
    Date of Patent: December 25, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chiao-Han Lee, Hsien-Yuan Liao, Ying-Ta Lu, Chi-Hsien Lin, Ho-Hsiang Chen, Tzu-Jin Yeh
  • Publication number: 20180204958
    Abstract: A semiconductor structure is provided. The semiconductor structure includes a floating substrate; and a capacitor grounded and connected to the floating substrate. A method of manufacturing a semiconductor structure is also provided.
    Type: Application
    Filed: March 15, 2018
    Publication date: July 19, 2018
    Inventors: HSIAO-TSUNG YEN, YU-LING LIN, CHIN-WEI KUO, HO-HSIANG CHEN, CHEWN-PU JOU, MIN-CHIE JENG