Patents by Inventor Ho-Hsiang Chen
Ho-Hsiang Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20160204282Abstract: A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.Type: ApplicationFiled: March 18, 2016Publication date: July 14, 2016Inventors: Chi-Hsien Lin, Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 9330830Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors.Type: GrantFiled: March 17, 2015Date of Patent: May 3, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Ying-Ta Lu, Huan-Neng Chen, Ho-Hsiang Chen
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Patent number: 9305888Abstract: Some embodiments relate to a semiconductor module having an integrated antenna structure that wirelessly transmits signals. The semiconductor module has a first die having a first far-back-end-of-the-line (FBEOL) metal layer with a ground plane connected to a ground terminal. A second die is stacked onto the first die and has a second FBEOL metal layer with an antenna exciting element that extends to a position that is vertically over the ground plane. One or more micro-bumps are vertically located between the first FBEOL metal layer and the second FBEOL metal layer. The one or more micro-bumps provide a radio frequency (RF) signal between the first FBEOL metal layer and the antenna exciting element of the second FBEOL metal layer. By using micro-bumps to connect the first and second die, the FBEOL metal layers are separated by a large spacing that provides for good performance of the integrated antenna structure.Type: GrantFiled: May 27, 2014Date of Patent: April 5, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Ho-Hsiang Chen
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Patent number: 9299699Abstract: A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.Type: GrantFiled: March 13, 2013Date of Patent: March 29, 2016Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chi-Hsien Lin, Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou, Fu-Lung Hsueh
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Patent number: 9293521Abstract: A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.Type: GrantFiled: August 8, 2014Date of Patent: March 22, 2016Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Ta Lu, Chi-Hsien Lin, Hsien-Yuan Liao, Ho-Hsiang Chen, Tzu-Jin Yeh
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Publication number: 20160049722Abstract: An antenna includes a plurality of upper electrodes in a first metal layer, a plurality of lower electrodes in a second metal layer, a plurality of side electrodes connecting the upper electrodes with the lower electrodes, and a ground structure. The upper electrodes, the lower electrodes and the side electrodes form one continuous electrode. The continuous electrode extends in a first direction away from a reference plane over a substrate. The upper electrodes extend in a second direction different from the first direction. The upper electrodes, the lower electrodes, and the side electrodes are embedded within a waveguide structure that includes a dielectric material. The substrate has a length extending in the first direction greater than a length the continuous electrode extends in the first direction. The waveguide structure includes a portion of the substrate in a region beyond the length of the continuous electrode in the first direction.Type: ApplicationFiled: October 28, 2015Publication date: February 18, 2016Inventors: Cheng-Hsien HUNG, Yu-Ling LIN, Ho-Hsiang CHEN
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Publication number: 20150364417Abstract: An integrated circuit comprises an inductor over a substrate and a guard ring surrounding the inductor. The guard ring comprises a plurality of first metal lines extending in a first direction and a plurality of second metal lines extending in a second direction. The second metal lines of the plurality of second metal lines are each coupled with at least one first metal line of the plurality of first metal lines. The guard ring also comprises a staggered line comprising a connected subset of at least one first metal line of the plurality of first metal lines and at least one second metal line of the plurality of second metal lines. The first metal lines of the plurality of first metal lines outside of the connected subset, the second metal lines of the plurality of second metal lines outside of the connected subset, and the staggered line surround the inductor.Type: ApplicationFiled: June 12, 2014Publication date: December 17, 2015Inventors: Chiao-Han LEE, Hsien-Yuan LIAO, Ying-Ta LU, Chi-Hsien LIN, Ho-Hsiang CHEN, Tzu-Jin YEH
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Patent number: 9209521Abstract: A rectangular helix antenna in an integrated circuit includes upper electrodes disposed in a first metal layer, lower electrodes disposed in a second metal layer, and side electrodes connecting the upper electrodes with the lower electrodes, respectively. The upper electrodes are disposed at an angle with respect to the lower electrodes. The upper electrodes, the lower electrodes, and the side electrodes form one continuous electrode spiraling around an inner shape of a rectangular bar. A micro-electromechanical system (MEMS) helix antenna has a similar structure to the rectangular helix antenna, but can have an inner shape of a bar.Type: GrantFiled: October 14, 2010Date of Patent: December 8, 2015Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Cheng-Hsien Hung, Yu-Ling Lin, Ho-Hsiang Chen
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Publication number: 20150325513Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.Type: ApplicationFiled: July 17, 2015Publication date: November 12, 2015Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
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Publication number: 20150325517Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.Type: ApplicationFiled: July 20, 2015Publication date: November 12, 2015Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng, Yu-Ling Lin
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Publication number: 20150316603Abstract: An apparatus includes three components. The first component includes a first transmission line; the second component is coupled with the first component and includes a second transmission line; and the third component electrically coupled with the first component and/or the second component. The transmission lines each include a substrate with a p-well or n-well within the substrate and a shielding layer over the p-well or n-well. The transmission lines also each include a plurality of intermediate conducting layers over the shielding layer, the plurality of intermediate conducting layers coupled by a plurality of vias. The transmission lines further each include a top conducting layer over the plurality of intermediate conducting layers.Type: ApplicationFiled: July 14, 2015Publication date: November 5, 2015Inventors: Hsiao-Tsung Yen, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu, Yu-Ling Lin
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Patent number: 9159718Abstract: A capacitor structure comprising semiconductor substrate and a matrix of capacitor units formed over the semiconductor substrate each capacitor unit. The matrix includes an interior structure comprised of one or more vertical plates, each vertical plate of the interior structure formed from a plurality of conductive portions connected vertically to each other, an exterior structure comprised of one or more vertical plates, each vertical plate of the exterior structure formed from a plurality of conductive portions connected vertically to each other, the exterior structure substantially encompassing the interior structure, and insulative material separating the interior and exterior structures. The structure also comprises a switching mechanism included in the capacitor structure to switch between ones of the plural capacitor units.Type: GrantFiled: March 8, 2013Date of Patent: October 13, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsiao-Tsung Yen, Ying-Ta Lu, Ho-Hsiang Chen, Chewn-Pu Jou
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Publication number: 20150255207Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors.Type: ApplicationFiled: March 17, 2015Publication date: September 10, 2015Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Ying-Ta Lu, Huan-Neng Chen, Ho-Hsiang Chen
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Publication number: 20150236644Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and a first, second, third, and fourth inductive elements. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The first and second inductive elements are electrically coupled to the first output nodes, respectively. The third inductive element is electrically coupled to one of the second output nodes and DC-biased and magnetically coupled to the first inductive element. The fourth inductive element is electrically coupled to the other of the second output nodes and DC-biased and magnetically coupled to the second inductive element.Type: ApplicationFiled: April 30, 2015Publication date: August 20, 2015Inventors: Ying-Ta LU, Hsien-Yuan LIAO, Chi-Hsien LIN, Hsiao-Tsung YEN, Ho-Hsiang CHEN, Chewn-Pu JOU
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Patent number: 9103884Abstract: A transmission line is provided. In one embodiment, the transmission line comprises a substrate, a well within the substrate, a shielding layer over the well, and a plurality of intermediate metal layers over the shielding layer, the plurality of intermediate metal layers coupled by a plurality of vias. The transmission line further includes a top metal layer over the plurality of intermediate metal layers. A test structure for de-embedding an on-wafer device, and a wafer are also disclosed.Type: GrantFiled: December 8, 2010Date of Patent: August 11, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Sa-Lly Liu
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Patent number: 9087840Abstract: A strip-line includes a ground plane extending through a plurality of dielectric layers over a substrate; a signal line over the substrate and on a side of the ground plane; a first plurality of metal strips under the signal line and in a first metal layer, wherein the first plurality of metal strips is parallel to each other, and is spaced apart from each other by spaces; and a second plurality of metal strips under the signal line and in a second metal layer over the first metal layer. The second plurality of metal strips vertically overlaps the spaces. The first plurality of metal strips is electrically coupled to the second plurality of metal strips through the ground plane, and no via physically contacts the first plurality of metal strips and the second plurality of metal strips.Type: GrantFiled: November 1, 2010Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yu-Ling Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chin-Wei Kuo, Chewn-Pu Jou
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Patent number: 9087838Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a semiconductor substrate having an integrated circuit (IC) device; an interconnect structure disposed on the semiconductor substrate and coupled with the IC device; and a transformer disposed on the semiconductor substrate and integrated in the interconnect structure. The transformer includes a first conductive feature; a second conductive feature inductively coupled with the first conductive feature; a third conductive feature electrically connected to the first conductive feature; and a fourth conductive feature electrically connected to the second conductive feature. The third and fourth conductive features are designed and configured to be capacitively coupled to increase a coupling coefficient of the transformer.Type: GrantFiled: October 25, 2011Date of Patent: July 21, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Chin-Wei Kuo, Ho-Hsiang Chen, Min-Chie Jeng
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Publication number: 20150145612Abstract: The present disclosure relates to a device and method to reduce voltage headroom within a voltage-controlled oscillator by utilizing trifilar coupling or transformer feedback with a capacitive coupling technique. In some embodiments of trifilar coupling, a VCO comprises cross-coupled single-ended oscillators, wherein the voltage of first gate within a first single-ended oscillator is separated from the voltage of a second drain within a second single-ended oscillator within the cross-coupled pair.Type: ApplicationFiled: February 3, 2015Publication date: May 28, 2015Inventors: Ying-Ta Lu, Hsien-Yuan Liao, Ho-Hsiang Chen, Chewn-Pu Jou
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Patent number: 9041477Abstract: An apparatus is disclosed that includes a first cross-coupled transistor pair, a second cross-coupled transistor pair, at least one capacitance unit, and an inductive unit. The first cross-coupled transistor pair and second cross-coupled transistor pair are coupled to a pair of first output nodes and a pair of second output nodes, respectively. The at least one capacitance unit is coupled to at least one of the pair of first output nodes and the pair of second output nodes. The inductive unit is coupled to the first cross-coupled transistor pair at the first output nodes and coupled to the second cross-coupled transistor pair at the second output nodes. The inductive unit generates mutual magnetic coupling between one of the first output nodes and one of the second output nodes and between the other of the first output nodes and the other of the second output nodes.Type: GrantFiled: June 14, 2013Date of Patent: May 26, 2015Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Ying-Ta Lu, Hsien-Yuan Liao, Chi-Hsien Lin, Hsiao-Tsung Yen, Ho-Hsiang Chen, Chewn-Pu Jou
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Patent number: 8981526Abstract: The present disclosure provides a semiconductor device. The semiconductor device includes a first inductor formed on a first substrate; a second inductor formed on a second substrate and conductively coupled with the first inductor as a transformer; and a plurality of micro-bump features configured between the first and second substrates. The plurality of micro-bump features include a magnetic material having a relative permeability substantially greater than one and are configured to enhance coupling between the first and second inductors.Type: GrantFiled: December 16, 2013Date of Patent: March 17, 2015Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Tsung Yen, Yu-Ling Lin, Ying-Ta Lu, Huan-Neng Chen, Ho-Hsiang Chen