Patents by Inventor Ho Jin Cho

Ho Jin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8470668
    Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
    Type: Grant
    Filed: December 28, 2010
    Date of Patent: June 25, 2013
    Assignee: SK Hynix Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Dong Kyun Lee
  • Publication number: 20130016239
    Abstract: A method and apparatus for removing a non-uniform motion blur using a multi-frame may estimate non-uniform motion blur information using a multi-frame including a non-uniform motion blur, and may remove the non-uniform motion blur using the estimated non-uniform motion blur and the multi-frame. The apparatus may also obtain more accurate non-uniform motion blur information by iteratively performing the estimation of the non-uniform motion blur information, and the removal of the non-uniform motion blur.
    Type: Application
    Filed: March 8, 2012
    Publication date: January 17, 2013
    Applicants: Postech Academy-Industry Foundation, Samsung Electronics Co., Ltd
    Inventors: Jung Uk CHO, Seung Yong LEE, Sung Hyun CHO, Shi Hwa LEE, Young Su MOON, Ho Jin CHO
  • Publication number: 20120208335
    Abstract: Methods of fabricating a semiconductor device are provided. The method includes forming a first gate stack and a second gate stack on a first region and a second region of a substrate, respectively. The method may further comprise forming first impurity regions self-aligned with the first gate stack and second impurity regions self-aligned with the second gate stack in the substrate of the first region and in the substrate of the second region, respectively. First impurity ions may be injected into the first and second impurity regions, forming a mask pattern covering the first region and exposing the second region on the substrate where the first impurity ions are injected and second impurity ions having an opposite conductivity type to the first impurity ions may be injected into the second impurity regions exposed by the mask pattern using a plasma doping process. The mask pattern may then be removed.
    Type: Application
    Filed: February 14, 2012
    Publication date: August 16, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Kyong Bong ROUH, Ho Jin CHO, Yong Soo JOUNG
  • Publication number: 20120098132
    Abstract: A semiconductor device with a stable structure having high capacitance by changing the pillar type storage node structure and a method of manufacturing the same are provided. The method includes forming a sacrificial layer on a semiconductor substrate including a storage node contact plug, etching the sacrificial layer to form a region exposing the storage node contact plug, forming a first conductive material within an inner side of the region, burying a second conductive material within the region in which the first conductive material is formed, and removing the sacrificial layer to form a pillar type storage node.
    Type: Application
    Filed: October 24, 2011
    Publication date: April 26, 2012
    Applicant: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan PARK, Ho Jin Cho, Dong Kyun Lee
  • Patent number: 8148764
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Grant
    Filed: July 19, 2011
    Date of Patent: April 3, 2012
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee
  • Publication number: 20120019980
    Abstract: An embodiment of the invention includes a pillar type capacitor where a pillar is formed over an upper portion of a storage node contact. A bottom electrode is formed over sidewalls of the pillar, and a dielectric film is formed over pillar and the bottom electrode. A top electrode is then formed over the upper portion of the dielectric film.
    Type: Application
    Filed: December 28, 2010
    Publication date: January 26, 2012
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Ho Jin CHO, Cheol Hwan PARK, Dong Kyun LEE
  • Publication number: 20110272784
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conducive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Application
    Filed: July 19, 2011
    Publication date: November 10, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Cheol Hwan PARK, Ho Jin CHO, Dong Kyun LEE
  • Patent number: 7985645
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Grant
    Filed: December 30, 2009
    Date of Patent: July 26, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Dong Kyun Lee
  • Patent number: 7906419
    Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.
    Type: Grant
    Filed: November 21, 2008
    Date of Patent: March 15, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Jae Soo Kim, Cheol Hwan Park, Ho Jin Cho
  • Publication number: 20110024874
    Abstract: A semiconductor device having a three-dimensional capacitor and a method for manufacturing the same is presented. The semiconductor device may have lower electrodes, a buffer layer, a dielectric layer, and an upper electrode. The lower electrodes are formed over a semiconductor substrate. The buffer layer is formed on sidewalls of the lower electrodes. The dielectric layer and an upper electrode are formed over semiconductor substrate including over the lower electrodes and the buffer layer. Accordingly, sufficient space between the lower electrodes can be secured. Furthermore, the lower electrodes can be each formed of a ruthenium layer and a titanium nitride layer and configured to have a pillar form. The dielectric layer may be composed of titanium dioxide.
    Type: Application
    Filed: December 28, 2009
    Publication date: February 3, 2011
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Cheol Hwan PARK, Ho Jin CHO, Dong Kyun LEE
  • Patent number: 7871939
    Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.
    Type: Grant
    Filed: December 28, 2007
    Date of Patent: January 18, 2011
    Assignee: Hynix Semiconductor Inc.
    Inventors: Gyu Dong Cho, Ho Jin Cho, Hyun Jung Kim
  • Publication number: 20100327410
    Abstract: A semiconductor device having a high aspect cylindrical capacitor and a method for fabricating the same is presented. The high aspect cylindrical type capacitor is a stable structure which is not prone to causing bunker defects and losses in a guard ring. The semiconductor device includes the cylindrical type capacitor structure, a storage node oxide, a guard ring hole, a conductive layer, and a capping oxide. The cylindrical type capacitor structure in a cell region includes a cylindrical type lower electrode, a dielectric and an upper electrode. The storage node oxide is in a peripheral region over the semiconductor substrate. The conductive layer coating the guard ring hole. The guard ring hole at a boundary of the peripheral region that adjoins the cell region over the semiconductor substrate. The capping oxide partially fills in a part of the conductive layer. The gapfill film filling in the rest of the conductive layer.
    Type: Application
    Filed: December 30, 2009
    Publication date: December 30, 2010
    Applicant: HYNIX SEMICONDUCTOR INC.
    Inventors: Cheol Hwan PARK, Ho Jin CHO, Dong Kyun LEE
  • Patent number: 7723183
    Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
    Type: Grant
    Filed: July 8, 2009
    Date of Patent: May 25, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Jae Soo Kim, Dong Kyun Lee
  • Patent number: 7688570
    Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.
    Type: Grant
    Filed: October 24, 2008
    Date of Patent: March 30, 2010
    Assignee: Hynix Semiconductor Inc.
    Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
  • Patent number: 7638407
    Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.
    Type: Grant
    Filed: November 6, 2008
    Date of Patent: December 29, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Cheol Hwan Park, Ho Jin Cho, Jae Soo Kim, Dong Kyun Lee
  • Publication number: 20090275186
    Abstract: Forming a capacitor of a semiconductor device includes forming an interlayer dielectric having holes over a semiconductor substrate. A conductive layer is then formed on surfaces of the holes and on the upper surface of the interlayer dielectric. A silicon-containing conductive layer is formed by flowing a silicon source gas for the semiconductor substrate formed with the conductive layer, so that silicon atoms can penetrate into the conductive layer. The silicon-containing conductive layer prevents etchant from infiltrating the interlayer dielectric below the silicon-containing conductive layer.
    Type: Application
    Filed: November 6, 2008
    Publication date: November 5, 2009
    Inventors: Cheol Hwan PARK, Ho Jin CHO, Jae Soo KIM, Dong Kyun LEE
  • Publication number: 20090269902
    Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
    Type: Application
    Filed: July 8, 2009
    Publication date: October 29, 2009
    Inventors: Ho Jin CHO, Cheol Hwan PARK, Jae Soo KIM, Dong Kyun LEE
  • Publication number: 20090246950
    Abstract: A laser annealing method for manufacturing a semiconductor device is presented. The method includes at least two forming steps and one annealing step. The first forming steps includes forming gates on a semiconductor substrate. The second forming step includes forming an insulation layer on the semiconductor substrate and on the gates. The annealing step includes annealing the insulation layer using electromagnetic radiation emitted from a laser.
    Type: Application
    Filed: November 21, 2008
    Publication date: October 1, 2009
    Inventors: Jae Soo KIM, Cheol Hwan PARK, Ho Jin CHO
  • Publication number: 20090206448
    Abstract: A semiconductor device that prevents the leaning of storage node when forming a capacitor having high capacitance includes a plurality of cylinder-shaped storage nodes formed over a semiconductor substrate; and support patterns formed to fix the storage nodes in the form of an ‘L’ or a ‘+’ when viewed from the top. This semiconductor device having support patterns in the form of an ‘L’ or a ‘+’ reduces stress on the storage nodes when subsequently forming a dielectric layer and plate nodes that prevents the capacitors from leaking.
    Type: Application
    Filed: October 2, 2008
    Publication date: August 20, 2009
    Inventors: Ho Jin CHO, Cheol Hwan PARK, Jae Wook SEO, Jong Kuk KIM
  • Patent number: 7576383
    Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.
    Type: Grant
    Filed: July 17, 2007
    Date of Patent: August 18, 2009
    Assignee: Hynix Semiconductor Inc.
    Inventors: Ho Jin Cho, Cheol Hwan Park, Jae Soo Kim, Dong Kyun Lee