Patents by Inventor Ho Jin Cho
Ho Jin Cho has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20090140385Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: October 24, 2008Publication date: June 4, 2009Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Patent number: 7463476Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: GrantFiled: June 7, 2005Date of Patent: December 9, 2008Assignee: Hynix Semiconductor Inc.Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Publication number: 20080194090Abstract: A method for manufacturing a semiconductor device for use in avoiding unwanted oxidation along exposed surfaces and for use in relieving etching damage is presented. The method includes step of forming sequentially a gate insulation layer, a polysilicon layer, a barrier layer, a metallic layer and a hard mask layer over a semiconductor substrate. The method also includes a step of etching the hard mask layer, the metallic layer, the barrier layer, the polysilicon layer and the gate insulation layer to form a gate. The method also includes a nitrifying step which uses a free radical is assisted chemical vapor deposition (RACVD) nitrifying process on surfaces of the layers forming the gate and a surface of the semiconductor substrate. The method also includes a step of subsequently performing a reoxidation process to the semiconductor substrate resultant that the RACVD nitrifying process is performed.Type: ApplicationFiled: December 28, 2007Publication date: August 14, 2008Inventors: Gyu Dong CHO, Ho Jin CHO, Hyun Jung KIM
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Publication number: 20080157093Abstract: A capacitor is made by forming a buffer oxide layer, an etching stop layer, and a mold insulation layer over a semiconductor substrate having a storage node contact plug. The mold insulation layer and the etching stop layer are etched to form a hole in an upper portion of the storage node contact plug. A tapering layer is deposited over the mold insulation layer including the hole. The tapering layer and the buffer oxide layer are etched back so that the tapering layer is remained only at the upper end portion of the etched hole. A metal storage node layer formed on the etched hole over the remaining tapering layer. The mold insulation layer and the remaining tapering layer are removed to form a cylindrical storage node having a tapered upper end. A dielectric layer and a plate node are formed over the storage node.Type: ApplicationFiled: July 17, 2007Publication date: July 3, 2008Inventors: Ho Jin CHO, Cheol Hwan PARK, Jae Soo KIM, Dong Kyun LEE
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Publication number: 20080070398Abstract: Disclosed herein is a method of fabricating a semiconductor device having a metal fuse. The method includes forming a plate electrode on a semiconductor substrate, forming an interlayer insulating layer on the plate electrode, forming a barrier metal layer containing either silicon or aluminum, a first metal layer and an antireflection layer containing either silicon or aluminum sequentially from bottom to top on the interlayer insulating layer. The method also includes patterning the antireflection layer, the first metal layer, and the barrier metal layer to form a first metal interconnection. The method also includes forming a fuse with the same material and structure as those of the first metal interconnection while forming the first metal interconnection.Type: ApplicationFiled: June 5, 2007Publication date: March 20, 2008Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Dong Su Park, Ho Jin Cho, Keum Bum Lee, Su Jin Chae, Cheol-Hwan Park
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Patent number: 7300852Abstract: A method for manufacturing a capacitor of a semiconductor element including: forming a bottom electrode of the capacitor on a semiconductor substrate; performing rapid thermal nitrification (RTN) on the upper surface of the bottom electrode; performing a thermal process on the obtained structure having the bottom electrode in a furnace under a nitride atmosphere to eliminate stress generated by the RTN; forming Al2O3 and HfO2 dielectric films on the nitrified bottom electrode; and forming a plate electrode of the capacitor on the Al2O3 and HfO2 dielectric films. The thermal process is performed after the RTN performed on the surface of the bottom electrode, so that stress, generated from the RTN, is alleviated, thereby allowing the capacitor to obtain a high capacitance and lowering leakage current.Type: GrantFiled: March 24, 2005Date of Patent: November 27, 2007Assignee: Hynix Semiconductor Inc.Inventors: Ho Jin Cho, Jun Soo Chang, Eun A. Lee, Su Jin Chae, Young Dae Kim
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Publication number: 20070264770Abstract: A method for forming a capacitor includes forming a concave mold over a semiconductor substrate. A storage node is formed on the concave mold. A dielectric layer including a zirconium oxide (ZrO2) layer is deposited over the storage node at a first temperature. A radical pile-up treatment on the dielectric layer is performed in an atmosphere including radicals at a second temperature higher than the first temperature to induce crystallization of the dielectric layer. A plate node is formed over the dielectric layer.Type: ApplicationFiled: December 30, 2006Publication date: November 15, 2007Applicant: Hynix Semiconductor, Inc.Inventors: Keum Bum Lee, Hai Won Kim, Ho Jin Cho, Jun Soo Chang, Eun A. Lee, Dong Su Park
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Patent number: 7208419Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.Type: GrantFiled: December 17, 2003Date of Patent: April 24, 2007Assignee: Hynix Semiconductor Inc.Inventors: Seung Woo Jin, Bong Soo Kim, Ho Jin Cho
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Publication number: 20060221548Abstract: A capacitor with nanotubes and a method for fabricating the same are provided. The capacitor includes: a lower electrode including a patterned conductive layer and a plurality of nanotubes formed on the patterned conductive layer in the shape of whiskers without using a catalytic layer; a dielectric layer formed on the lower electrode; and an upper electrode formed on the dielectric layer. The method includes the steps of: forming a conductive layer for forming a lower electrode; forming a nanotube array including a plurality of nanotubes formed on the conductive layer without using a catalytic layer; forming a dielectric layer on the nanotube array; and forming an upper electrode on the dielectric layer.Type: ApplicationFiled: June 7, 2005Publication date: October 5, 2006Inventors: Eun-A Lee, Ho-Jin Cho, Young-Dae Kim, Jun-Soo Chang, Su-Jin Chae, Hai-Won Kim
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Patent number: 6955974Abstract: A method for forming an isolation layer of a semiconductor device, which comprises the steps of: a) sequentially forming a pad oxide layer and a pad nitride layer on a silicon substrate; b) etching the pad nitride layer, the pad oxide layer, and the silicon substrate, thereby forming a trench; c) thermal-oxidizing the resultant substrate to form a sidewall oxide layer on a surface of the trench; d) nitrifying the sidewall oxide layer through the use of NH3 annealing; e) depositing a liner aluminum nitride layer on an entire surface of the silicon substrate inclusive of the nitrated sidewall oxide layer; f) depositing a buried oxide layer on the liner aluminum nitride layer to fill the trench; g) performing a chemical mechanical polishing process with respect to the buried oxide layer; and h) eliminating the pad nitride layer.Type: GrantFiled: June 25, 2004Date of Patent: October 18, 2005Assignee: Hynix Semiconductor Inc.Inventors: Tae Hyeok Lee, Cheol Hwan Park, Dong Su Park, Ho Jin Cho, Eun A Lee
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Patent number: 6841925Abstract: Disclosed is a deflection yoke comprising: a fastening band of a ring shape assembled on an outer periphery of a neck portion in a coil separator by a fixing manner, provided for being extended and contracted; a pair of flanges bent and extended from both ends of the fastening band, on which a through hole is formed; a yoke clamp for generating fastening force by tightening of a bolt for passing through a pair of through holes, then being tightened by a nut; a bending portion projected on an outer side along the periphery of the fastening band, whose object contact plane for coming in contact with an outer periphery of the neck portion is divided into at least two or more.Type: GrantFiled: December 19, 2002Date of Patent: January 11, 2005Assignee: Samsung Electro-Mechanics, Co., Ltd.Inventors: Song Geun Lee, Ho Jin Cho, Kwang Yun Choi
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Patent number: 6800567Abstract: A method for forming a polyatomic layer with a mixed deposition method consisting of an atomic layer deposition method (ALD) and a chemical vapor deposition method. The mixed deposition method can be adopted to form a polyatomic high dielectric layer, such as BST or STO. Accordingly, it is possible to form a polyatomic high dielectric layer having a uniform composition distribution, and thereby also having a high dielectric characteristic and a low leakage current characteristic.Type: GrantFiled: August 22, 2002Date of Patent: October 5, 2004Assignee: Hynix Semiconductor Inc.Inventor: Ho Jin Cho
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Publication number: 20040161936Abstract: The present invention relates to a method for fabricating a semiconductor device. The method comprises the steps of: forming a gate line on a semiconductor substrate; forming a buffer layer and a spacer nitride film on the entire surface of the substrate including the gate line; selectively etching the buffer layer and the spacer nitride film in such a manner that they remain on both sides of the gate line; performing an ion implantation process using the remaining buffer layer and spacer nitride film as a barrier film to form junction regions in the semiconductor substrate at both sides of the gate line; forming an interlayer insulating film on the entire upper portion of the resulting substrate; selectively removing the interlayer insulating film to form contact holes exposing the upper surface of the junction regions; and forming contact plugs in the contact holes.Type: ApplicationFiled: December 17, 2003Publication date: August 19, 2004Inventors: Seung Woo Jin, Bong Soo Kim, Ho Jin Cho
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Publication number: 20040137678Abstract: A method for forming capacitor of semiconductor device wherein a stacked structure of Al-rich HfO2—Al2O3 film and Hf-rich HfO2—Al2O3 film or a stacked structure of Al2O3 film and Hf-rich HfO2—Al2O3 film is used as a dielectric film is disclosed. The method comprises (a) forming an oxide film on an interlayer insulating film having a storage electrode contact plug; (b) selectively etching the oxide film to form an opening exposing the top surface of the storage electrode contact plug; (c) forming a conductive layer on the bottom and the inner walls of the opening; (d) removing the oxide film to form a storage electrode; (e) forming a dielectric film having a stacked structure of Al-rich HfO2—Al2O3 film and Hf-rich HfO2—Al2O3 film on the surface of the storage electrode; (f) annealing the dielectric film; and (g) forming a plate electrode on the dielectric film.Type: ApplicationFiled: June 30, 2003Publication date: July 15, 2004Inventors: Ho Jin Cho, Seung Woo Jin, Bong Soo Kim
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Publication number: 20040126946Abstract: A method for forming a transistor of a semiconductor device wherein a deposition of a buffering oxide film prior to deposition of a nitride film for a gate spacer is performed at a low temperature to prevent out-diffusion of impurities implanted in a source/drain region, thereby providing a semiconductor device with low contact resistance for a bitline and a storage electrode is disclosed. The method for forming a transistor of a semiconductor device comprises the steps of: forming a gate electrode on a semiconductor substrate; ion-implanting impurities into the semiconductor substrate using the gate electrode as a mask to form a source/drain junction region; forming an oxide film on the resulting structure at a temperature below 700° C.; and forming a nitride film spacer on a sidewall of the gate electrode.Type: ApplicationFiled: June 30, 2003Publication date: July 1, 2004Inventors: Bong Soo Kim, Seung Woo Jin, Ho Jin Cho
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Patent number: 6685522Abstract: Disclosed is a product quality test in a winding step of the entire manufacturing process of a deflection yoke, which is a core part of a display device employing a cathode ray tube such as a color TV or a monitor, and in particular, a winding zig for measuring magnetic fields of a deflection yoke and a magnetic field measuring system of a deflection yoke using the winding zig.Type: GrantFiled: June 8, 2001Date of Patent: February 3, 2004Assignee: Samsung Electro-Mechanics Co., Ltd.Inventors: In Jung Yun, Ho Jin Cho, Bong Woo Lee, Byung Hoon Kang, Kwang Yun Choi
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Publication number: 20030227245Abstract: Disclosed is a deflection yoke comprising: a fastening band of a ring shape assembled on an outer periphery of a neck portion in a coil separator by a fixing manner, provided for being extended and contracted; a pair of flanges bent and extended from both ends of the fastening band, on which a through hole is formed; a yoke clamp for generating fastening force by tightening of a bolt for passing through a pair of through holes, then being tightened by a nut; a bending portion projected on an outer side along the periphery of the fastening band, whose object contact plane for coming in contact with an outer periphery of the neck portion is divided into at least two or more.Type: ApplicationFiled: December 19, 2002Publication date: December 11, 2003Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: Song Geun Lee, Ho Jin Cho, Kwang Yun Choi
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Publication number: 20030040162Abstract: Disclosed is a method for fabricating a capacitor, comprising the steps of forming a bottom electrode on the semiconductor substrate by an electro chemical deposition (ECD) technique, performing a wet-cleaning process for removing impurities of a surface of the bottom electrode, forming a dielectric layer on the bottom electrode and forming a top electrode on the dielectric layer.Type: ApplicationFiled: August 19, 2002Publication date: February 27, 2003Applicant: HYNIX SEMICONDUCTOR INC.Inventors: Ho-Jin Cho, Hyung-Bok Choi
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Publication number: 20030040197Abstract: A method for forming a polyatomic layer with a mixed deposition method consisting of an atomic layer deposition method (ALD) and a chemical vapor deposition method. The mixed deposition method can be adopted to form the polyatomic high dielectric layer, such as BST or STO. Accordingly, it is possible to form a polyatomic high dielectric layer having a uniform composition distribution, and thereby a high dielectric characteristic and a leakage current characteristic are may be improved.Type: ApplicationFiled: August 22, 2002Publication date: February 27, 2003Applicant: HYNIX SEMICONDUCTOR INC.Inventor: Ho-Jin Cho
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Publication number: 20020164915Abstract: Disclosed is a product quality test in a winding step of the entire manufacturing process of a deflection yoke, which is a core part of a display device employing a cathode ray tube such as a color TV or a monitor, and in particular, a winding zig for measuring magnetic fields of a deflection yoke and a magnetic field measuring system of a deflection yoke using the winding zig.Type: ApplicationFiled: June 8, 2001Publication date: November 7, 2002Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.Inventors: In Jung Yun, Ho Jin Cho, Bong Woo Lee, Byung Hoon Kang, Kwang Yun Choi