Abstract: A method of managing data access of a storage medium includes establishing an address mapping table to record a physical address of a first data stored in the storage medium, where the physical address of the first data is mapped to a logical address of the first data; and when receiving a command for handling the first data stored in the storage medium internally, processing the address mapping table to serve the command without physically accessing the first data stored in the storage medium.

Abstract: A header region protection apparatus of an optical storage medium. The apparatus comprises an encoder, a header location generator, and a header protector. The encoder converts user data to an EFM signal and a write enable signal according to a write clock. The header location generator generates a header location signal. The header protector is coupled to the encoder and the header location generator and generates a header protect write enable signal according to the write enable signal and the header location signal.

Abstract: A method for controlling a storage system and the storage system using this method are disclosed. In the storage system, at least two memory units share an I/O bus. The shared I/O bus transfers information for each memory unit to execute an operation. The operation has at least one high priority cycle and at least one low priority cycle. When a low priority cycle is overlapped with a high priority cycle, the low priority cycle is suspended, and the high priority cycle is operated first. After the high priority cycle is finished, the suspended low priority cycle is then resumed. By doing so, the shared I/O bus may be used by one memory unit during a busy cycle for another memory unit, during which the latter memory unit does not use the I/O bus. Therefore, the I/O bus can be more efficiently used.

Abstract: The invention provides a method for performing copy back operations. First, a copy back command is sent to a flash memory for reading a first error correction code (ECC) data from a first address. The first ECC data is then received from the flash memory. The first ECC data is then decoded without performing error correction to calculate a fail count of the first ECC data. The fail count is then compared with a first threshold value. When the fail count is less than the first threshold value, a first program command is sent to the flash memory for storing the first ECC data to a second address of the flash memory. When the fail count is less than the first threshold value, the first ECC data is not sent back to the flash memory.

Abstract: One exemplary storage control device for a storage medium includes a controller and a voltage detector, where the controller controls data access of the storage medium, and the voltage detector monitors a power signal and asserts a detection signal to notify the controller when anomaly of the power signal is detected. Another exemplary storage control device for a storage medium includes a voltage detector and a controller, where the voltage detector monitors a power signal to generate a detection signal, and the controller controls data access of the storage medium. In addition, the controller enters a first operational state when the detection signal indicates that a voltage level of the power signal falls within a first voltage range, and enters a second operational state when the detection signal indicates that the voltage level of the power signal falls within a second voltage range.

Abstract: A flash memory device includes a memory array and a memory control circuit. The memory array includes memory modules. Each memory module is located in a memory channel and includes a predetermined number of memory cells. The memory control circuit is coupled to the memory array via an address latch enable (ALE) pin and a command latch enable (CLE) pin. The ALE pin and the CLE pin are coupled to all of the memory cells and shared by all of the memory cells in the memory array.

Abstract: Methods for updating and recovering user data of a non-volatile memory array such as a flash memory are disclosed. An indication for indicating a mapping relationship for a logical address is established when original user data of the logical addresses is updated into new user data. The indication records new pointers, which record the mapping relationships between logical addresses and physical addresses storing the new user data of the logical addresses. Alternatively, the indication records memory positions of the non-volatile memory array which are defined as designated memory positions and a sequence for using these designated memory positions.

Abstract: Methods and apparatuses for generating error correction codes of a data block are disclosed. One proposed method includes: storing a plurality of calculating data corresponding to the error correction codes in a buffer; generating operating results according to the calculating data from the buffer and corresponding data of the data block; writing operating results into the buffer; and generating a plurality of updated calculating data according to the operating results stored in the buffer.

Abstract: A recording apparatus and a recording method are provided. Control information is generated by the microcontroller based on the received command. The data preparing unit has a control register and a preparing circuit, wherein the control register is used for storing a set of control register values corresponding to the control information, and the preparing circuit is used for generating prepared data based on the set of control register values and storing the prepared data in the data buffer. The recording circuit records on an optical storage media based on the prepared data. The optical storage media has a lead-in area having a plurality of continuous zones. The prepared data includes a plurality of data to be written into the corresponding zones and the plurality of data are stored in the data buffer in the same sequence as the writing sequence to the zones and are read continuously.

Abstract: A data recording method for an optical disk drive is implemented by the following steps. First, one or more data blocks are encoded and recorded sequentially, and it detects if a buffer under run occurs. If a buffer under run occurs, the recording does not stop immediately until at least the main data of the data block being currently recorded have been recorded completely. Afterwards, it restarts to encode and record from the data block next to the data block where the recording stops. Moreover, the recording also can stops if a servo error is detected, and the data restart to encode and record from the data block where the recording stops or at least one data block preceding the data block where the recording stops.

Abstract: The invention provides a flash device. In one embodiment, the flash device comprises a first NAND flash integrated circuit, a second NAND flash integrated circuit, and a control integrated circuit. The control integrated circuit generates a plurality of first access signals with first timings to access the first NAND flash IC, and generates a plurality of second access signals with second timings to access the second NAND flash IC, wherein the first timings are different from the second timings. The first NAND flash integrated circuit then accesses data stored therein according to the first access signals. The second NAND flash integrated circuit then accesses data stored therein according to the second access signals.

Abstract: An optical recording device records data on an optical storage medium. The device generates a data-interrupted address and reconnects the interrupted data from a data-reconnecting address so as to enable further correct reading of the interrupted data. The device comprises an addressing module for providing a reference address on the storage medium as a reference address; a recording-interrupted generator for detecting a recording-interrupted condition and generating a recording-interrupted signal; a data recording module for recording and suspending recording the data according to the recording-interrupted signal, and reconnecting the data according to a data-reconnecting address and the reference address; a data-interrupted address generator for generating the data-interrupted address; a data-reconnecting address generator for generating the data-reconnecting address.

Abstract: A channel bit detection system is provided. The channel bit detection system includes an RF front end, an analog-to-digital converter, a combiner, a length estimator, a length accumulator, an offset control, and a channel bit detector. The RF front end receives an RF signal, and is then digitized at a sampling rate R into a plurality of samples by the analog-to-digital converter. The combiner produces combined samples by shifting the plurality of samples an offset value. The length estimator estimates a length of each two consecutive combined samples. The length accumulator produces land lengths and pit lengths of the combined samples according to length of each two consecutive combined samples. The offset control provides the offset value according to the land lengths and the pits lengths. The channel bit detector recovers the channel bit from the plurality of combined samples.

Abstract: A system including a pulse generating module and a processing module is disclosed. The pulse generating module generates a target signal. The processing module outputs a processing signal according to the target signal. Throughput of the target signal exceeds throughput of the processing signal.

Abstract: An integrated circuit package comprising a semiconductor device and pins is provided. The semiconductor device comprises first and second scan chains, each having an input port and an output port. The semiconductor device further comprises at least two first pads, at least two second pads, and a connecting device. The at least two first pads are coupled to the input port of the first scan chain and the output port of the second scan chain, respectively. The at least two second pads are coupled to the output port of the first scan chain and the input port of the second scan chain, respectively. The connecting device is coupled between the first and the second chains, and is capable of controlling electrical connection between the input port of the second scan chain and the output port of the first scan chain. When the connecting device is disabled, the input port of the second scan chain is electrically disconnected from the output port of the first scan chain.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A system and method for printing a visible image onto an optical disc through tuning a driving signal of an optical pick-up unit are disclosed. The system includes a driving circuit, coupled to the optical pick-up unit, for providing a driving signal to drive the optical pick-up unit; and an adjusting circuit, coupled to the driving circuit, for controlling the driving circuit to adjust the driving signal according to a rotation source signal corresponding to a rotation of the optical disc.

Abstract: A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.

Abstract: This invention provides an optical storage device for recording a plurality of data onto an optical storage medium. If recording interrupted, the optical storage device generates a data-interrupted address, and re-connects the interrupted data with a data re-connecting physical address. The optical storage device comprises a physical addressing module, a record-interrupt generator, a data recording controller, a data-interrupt address generator and a data-reconnecting physical address generator. The physical addressing module provides a reference physical address for recording data onto the optical storage medium. When detecting the interrupt of data recording, the data-interrupt address generator generates the address of the interrupted data. According to the address of the interrupted data, the data-reconnecting physical address generator generates a data-reconnecting physical address.

Abstract: The present invention sets forth an interface method and system for host acceleration between an electronic device and a host PC. The system comprises an acceleration unit for rapidly classifying a type of an host command then issuing a flag signal to a microprocessor. The microprocessor then executes corresponding actions according to the flag signal and the host command without parsing the host command for accelerating the data communication between the device and a host PC.