Abstract: A recording method and drive for optical storage media. The method inserts or replaces a special pattern in a recording EFM signal before the recording process is interrupted. Therefore, the special pattern is recorded either before or on the interrupted position. The starting position of the succeeding recording process is located by searching for the special pattern.

Abstract: Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns of the data block, and Y is greater than or equal to 2. A second buffer stores Y partial-parity columns. An encoder is used for encoding the first section read from the first buffer to generate the partial-parity columns, and then storing the partial-parity columns in the second buffer. The second section read from the first buffer and the partial-parity columns read from the second buffer are encoded to generate updated partial-parity columns. Next, the partial-parity columns in the second buffer are updated by storing the updated partial-parity columns.

Abstract: An integrated circuit (IC) for being applied to an electronic device includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to another IC for testing. A testing system includes at least one testing device and a plurality of ICs that are tested by the testing device. The ICs are coupled to the testing device. Each IC of the ICs is for being applied to an electronic device and includes: a control circuit for controlling the electronic device; and a signal generation unit coupled to the control circuit for generating at least one signal inside the IC as an output signal and outputting the output signal to one of the other IC(s) for testing.

Abstract: Methods and systems for generating ECC encode a data block to generate corresponding error correction codes. A first buffer sequentially stores a first section and a second section of the data block, wherein each of the first and second sections is composed of X data rows and Y data columns of the data block, and Y is greater than or equal to 2. A second buffer stores Y partial-parity columns. An encoder is used for encoding the first section read from the first buffer to generate the partial-parity columns, and then storing the partial-parity columns in the second buffer. The second section read from the first buffer and the partial-parity columns read from the second buffer are encoded to generate updated partial-parity columns. Next, the partial-parity columns in the second buffer are updated by storing the updated partial-parity columns.

Abstract: An error correction code generator uses an additional static random access memory (SRAM) or a multi-symbol encoder to improve the encoding efficiency. During the encoding operation, the number of the data access of the dynamic random access memory (DRAM) with the row address switching can be reduced considerably via using the additional SRAM or multi-symbol encoder. Hence, the efficiency of the data access of the DRAM is improved and the encoding time of the error correction code generator is reduced.

Abstract: This invention provides an optical storage device for recording a plurality of data onto an optical storage medium. If recording interrupted, the optical storage device generates a data-interrupted address, and re-connects the interrupted data with a data re-connecting physical address. The optical storage device comprises a physical addressing module, a record-interrupt generator, a data recording controller, a data-interrupt address generator, and a data-reconnecting physical address generator. The physical addressing module provides a reference physical address for recording data onto the optical storage medium. When detecting the interrupt of data recording, the data-interrupt address generator generates the address of the interrupted data. According to the address of the interrupted data, the data-reconnecting physical address generator generates a data-reconnecting physical address.

Abstract: A testing method utilizing at least one signal between ICs includes: coupling at least one testing device to a plurality of ICs that are capable of being tested by the testing device, the ICs including at least a first IC and a second IC; coupling the second IC to the first IC to utilize at least one output signal of the first IC to be at least one input signal of the second IC; and testing the second IC by utilizing the testing device and the output signal of the first IC.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: A system and method of controlling data recording process of optical recording medium by adjusting writing signal to record the adjusted writing signal on the optical recording medium in a sequential writing are described. The control system for controlling a recording process of an optical recording medium comprises an information unit, a data-preparing unit and a recording controller. The information unit generates an information signal. The data-preparing unit is coupled to the information unit receives data from a data source and prepares the data for recording. The data is then transformed into a writing signal according to the information signal. The recording controller coupled to the information unit and the data-preparing unit controls the data-preparing unit to adjust the writing signal while acquiring the information signal from the information unit during a sequential writing. Thus, the recording controller adjusts the writing signal according to the information signal.

Abstract: A phase locked loop (PLL) for generating an output signal according to an input signal is disclosed. The PLL of the present invention includes a detector for generating a detection signal according to the logical difference between the input signal and a feedback signal, a signal mixer electrically connected to the detector for generating a control signal according to the detection signal and a mixing reference signal, a filtering device electrically connected to the signal mixer for generating an adjust signal according to the control signal, a controllable oscillator electrically connected to the filtering device for generating the output signal according to the adjust signal, and a frequency divider electrically connected to the controllable oscillator for generating the feedback signal and the mixing reference signal according to the output signal. The frequency of the output signal is at least twice the frequency of the input signal.

Abstract: A header region protection apparatus of an optical storage medium. The apparatus comprises an encoder, a header location generator, and a header protector. The encoder converts user data to an EFM signal and a write enable signal according to a write clock. The header location generator generates a header location signal. The header protector is coupled to the encoder and the header location generator and generates a header protect write enable signal according to the write enable signal and the header location signal.

Abstract: A data recording method for an optical disk drive is implemented by the following steps. First, one or more data blocks are encoded and recorded sequentially, and it detects if a buffer under run occurs. If a buffer under run occurs, the recording does not stop immediately until at least the main data of the data block being currently recorded have been recorded completely. Afterwards, it restarts to encode and record from the data block next to the data block where the recording stops. Moreover, the recording also can stops if a servo error is detected, and the data restart to encode and record from the data block where the recording stops or at least one data block preceding the data block where the recording stops.

Abstract: A clock rate adjustment apparatus and a method for adjusting a clock rate of a clock for an optical storage system are provided. The clock rate adjustment apparatus comprises an indication provider, a throughput rate detector, and a clock generator. The method performs the following steps. The indication provider generates an indicatory signal indicating a state of the optical storage system. The throughput rate detector generates a control signal in response to the indicatory signal. The clock generator generates the clock at the clock rate in response to the control signal. The clock rate determined by the clock rate adjustment apparatus may be adjusted dynamically in response to a required minimum clock rate and a variable data rate.

Abstract: A PLL system for generating an output signal according to a first reference signal is disclosed. The PLL system includes a clock generator to generate the output signal according to a phase difference between the first reference signal and the frequency-divided signal; and a phase-shift detector for detecting a position difference between the physical address and an updated logical address of the recording data to generate a phase adjusting signal. The PLL system also includes an adder for updating a detected logical address with a random value to output the updated logical address to the position difference detector; and a phase-controllable frequency divider for generating the frequency-divided signal and for receiving the phase adjusting signal to adjust the phase of the frequency-divided signal.

Abstract: A data recording method for an optical disk drive is implemented by the following steps. First, one or more data blocks are encoded and recorded sequentially, and it detects if a buffer under run occurs. If a buffer under run occurs, the recording does not stop immediately until at least the main data of the data block being currently recorded have been recorded completely. Afterwards, it restarts to encode and record from the data block next to the data block where the recording stops. Moreover, the recording also can stops if a servo error is detected, and the data restart to encode and record from the data block where the recording stops or at least one data block preceding the data block where the recording stops.

Abstract: A phase locked loop (PLL) system for generating a reference clock to write recording data on an optical medium includes a clock generator generating the reference clock according to a phase difference between the reference signal and a first frequency-divided signal; a phase-shift detector generating a phase adjusting signal; and a phase-controllable frequency divider dividing the frequency of the reference clock to generate the first frequency-divided signal, and receiving the phase adjusting signal to adjust the phase of the first frequency-divided signal. The phase-shift detector includes an ADIP sync detector generating an ADIP synchronization signal synchronous to the ADIP units of the optical medium; a frequency divider dividing the reference clock to generate a second frequency-divided signal; and a phase difference detector detecting a phase difference between the second frequency-divided signal and the ADIP synchronization signal to generate the phase adjusting signal.

Abstract: In a process for recording a data onto an optical storage medium which includes a fault correction mechanism, a detection system is preferably coupled to an optical data recorder comprising a data generating device and a data reading device. The data generating device generates the recorded data. The data reading device reads a reflection signal from the optical storage medium and generates a read-out signal to the determination device. A reflection signal is read from the medium to detect whether the recorded data can be reliably read out under this mechanism. A determination device of the detection system outputs a faulted data information signal in responsive to the reflection signal based on rules of the fault correction mechanism. The determination device further comprises a fault detection module. The fault detection module would receive the read-out signal and output a write fault signal as the faulted data information signal.

Abstract: A recording apparatus and a recording method are provided. Control information is generated by the microcontroller based on the received command. The data preparing unit has a control register and a preparing circuit wherein the control register is used for storing a set of control register values corresponding to the control information, and the preparing circuit is used for generating prepared data based on the set of control register values and storing the prepared data in the data buffer. The recording circuit records on an optical storage media based on the prepared data. The optical storage media has a lead-in area having a plurality of continuous zones. The prepared data includes a plurality of data to be written into the corresponding zones and the plurality of data are stored in the data buffer in the same sequence as the writing sequence to the zones and are read continuously.

Abstract: An ACS circuit and a Viterbi decoder with the circuit. The Add-Compare-Select (ACS) circuit comprises: two registers for storing two previous candidate state metrics; a first adder for adding the value stored in the first register and a first branch metric to generate a first addition result; a second adder for adding the value stored in the second register and the first branch metric to generate a second addition result; a comparator for comparing the values stored in the first register and the second register to generate a decision bit; and a multiplexer for selecting either the first addition result or the second addition result as a new output candidate state metric according to the decision bit. Due to the parallel processing of the adders and the comparator, the processing speed of a Viterbi decoder with the ACS will be increased.

Abstract: A PRML system with a branch estimator. The PRML system includes an analog-to-digital converter (ADC) for receiving an analog input signal and converting the analog input signal into a digital sampled signal according a sampling clock; a branch estimator for receiving the digital sampled signal and estimating each branch eigenvalue; and a Viterbi decoder for decoding an output signal according to the digital sampled signal and the branch eigenvalues. Since the PRML system employs the branch estimator to estimate the branch eigenvalues of trellis of the Viterbi decoder directly, the PRML system can be simplified and the execution speed of the PRML system can be increased.