Patents by Inventor Hong Lin

Hong Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240157691
    Abstract: A film laminating apparatus and an electrode sheet processing device are disclosed. The film laminating apparatus includes a frame, a conveying mechanism, a mounting plate, and a plurality of film laminating mechanisms, the plurality of film laminating mechanisms being mounted on the mounting plate; the conveying mechanism being mounted on the frame and being capable of conveying an electrode sheet in a first direction into the film laminating apparatus; and the mounting plate being mounted on the frame and forming an included angle with the first direction. The plurality of film laminating mechanisms are tilted or vertically arranged relative to the conveying direction of an electrode sheet. The space occupied by the plurality of film laminating mechanisms, the size of the film laminating apparatus, the volume of the film laminating apparatus, and the space occupied by the film laminating apparatus in the conveying direction of the electrode sheet is reduced.
    Type: Application
    Filed: November 8, 2023
    Publication date: May 16, 2024
    Applicant: CONTEMPORARY AMPEREX TECHNOLOGY CO., LIMITED
    Inventors: Lei SONG, Hong LIN, Mou ZENG, Guangcheng ZHONG, Ningbo DU, Jinlong HUANG, Pengpeng WANG
  • Patent number: 11982866
    Abstract: An optical element driving mechanism is provided and includes a fixed assembly, a movable assembly, a driving assembly and a stopping assembly. The fixed assembly has a main axis. The movable assembly is configured to connect an optical element, and the movable assembly is movable relative to the fixed assembly. The driving assembly is configured to drive the movable assembly to move relative to the fixed assembly. The stopping assembly is configured to limit the movement of the movable assembly relative to the fixed assembly within a range of motion.
    Type: Grant
    Filed: December 15, 2022
    Date of Patent: May 14, 2024
    Assignee: TDK TAIWAN CORP.
    Inventors: Chao-Chang Hu, Liang-Ting Ho, Chen-Er Hsu, Yi-Liang Chan, Fu-Lai Tseng, Fu-Yuan Wu, Chen-Chi Kuo, Ying-Jen Wang, Wei-Han Hsia, Yi-Hsin Tseng, Wen-Chang Lin, Chun-Chia Liao, Shou-Jen Liu, Chao-Chun Chang, Yi-Chieh Lin, Shang-Yu Hsu, Yu-Huai Liao, Shih-Wei Hung, Sin-Hong Lin, Kun-Shih Lin, Yu-Cheng Lin, Wen-Yen Huang, Wei-Jhe Shen, Chih-Shiang Wu, Sin-Jhong Song, Che-Hsiang Chiu, Sheng-Chang Lin
  • Publication number: 20240151994
    Abstract: A directional coupler is configured to receive a continuous light waveform and split the waveform into two carrier signals. Ring modulators are configured to receive the carrier signals and binary data and modulate the carrier signals based on the binary data. A combiner is configured to combine the modulated carrier signals into a four-level pulse amplitude modulation (PAM4) signal.
    Type: Application
    Filed: January 12, 2024
    Publication date: May 9, 2024
    Inventors: Chih-Chang LIN, Chan-Hong CHERN
  • Publication number: 20240149207
    Abstract: A system and method for clean and low-carbon in-situ disposal of waste incineration fly ash includes a waste incineration system and a fly ash disposal system. The fly ash disposal system includes a water washing system, an MVR system, and a dioxin removal system. The water washing system includes a water washing device and a press filtering device. The dioxin removal system includes a heating device, an activated carbon adsorption device, and a heat pump system. The MVR system includes a crystallizer, a heater, a vapor compressor, and other equipment. The waste incineration system is coupled with the fly ash disposal system nearby to achieve in-situ disposal of fly ash, avoiding the logistics cost and secondary pollution problems of long-distance transportation of fly ash, and greatly reducing energy and water resource consumption.
    Type: Application
    Filed: November 2, 2023
    Publication date: May 9, 2024
    Inventors: Xiaoqing Lin, Jie Chen, Hong Yu, Xiaodong Li, Jianhua Yan
  • Patent number: 11979158
    Abstract: An integrated circuit (IC) device includes a master latch circuit having a first clock input and a data output, a slave latch circuit having a second clock input and a data input electrically coupled to the data output of the master latch circuit, and a clock circuit. The clock circuit is electrically coupled to the first clock input by a first electrical connection configured to have a first time delay between the clock circuit and the first clock input. The clock circuit is electrically coupled to the second clock input by a second electrical connection configured to have a second time delay between the clock circuit and the second clock input. The first time delay is longer than the second time delay.
    Type: Grant
    Filed: May 26, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-Yu Lin, Yung-Chen Chien, Jia-Hong Gao, Jerry Chang Jui Kao, Hui-Zhong Zhuang
  • Patent number: 11978511
    Abstract: A phase-change memory (PCM) cell is provided to include a first electrode, a second electrode, and a phase-change feature disposed between the first electrode and the second electrode. The phase-change feature is configured to change its data state based on a write operation performed on the PCM cell. The write operation includes a reset stage and a set stage. In the reset stage, a plurality of reset current pulses are applied to the PCM cell, and the reset current pulses have increasing current amplitudes. In the set stage, a plurality of set current pulses are applied to the PCM cell, and the set current pulses exhibit an increasing trend in current amplitude. The current amplitudes of the set current pulses are smaller than those of the reset current pulses.
    Type: Grant
    Filed: January 21, 2022
    Date of Patent: May 7, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung-Huei Lee, Chun-Wei Chang, Jian-Hong Lin, Wen-Hsien Kuo, Pei-Chun Liao, Chih-Hung Nien
  • Publication number: 20240145455
    Abstract: An electronic package is provided, in which an electronic module including a first electronic element and a second electronic element is disposed on a carrier structure embedded with a third electronic element, and the third electronic element is a photonic chip electrically connected to the electronic module. Therefore, with this configuration, it is beneficial to reduce a layout area of the carrier structure to meet the requirement of miniaturization.
    Type: Application
    Filed: January 17, 2023
    Publication date: May 2, 2024
    Applicant: SILICONWARE PRECISION INDUSTRIES CO., LTD.
    Inventors: Meng-Jie LEE, Chih-Nan LIN, Ci-Hong YAN, Nai-Hao KAO
  • Patent number: 11972826
    Abstract: Disclosed herein are related to a system and a method of extending a lifetime of a memory cell. In one aspect, a memory controller applies a first pulse having a first amplitude to the memory cell to write input data to the memory cell. In one aspect, the memory controller applies a second pulse having a second amplitude larger than the first amplitude to the memory cell to extend a lifetime of the memory cell. The memory cell may include a resistive memory device or a phase change random access memory device. In one aspect, the memory controller applies the second pulse to the memory cell to repair the memory cell in response to determining that the memory cell has failed. In one aspect, the memory controller periodically applies the second pulse to the memory cell to extend the lifetime of the memory cell before the memory cell fails.
    Type: Grant
    Filed: July 8, 2021
    Date of Patent: April 30, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Huei Lee, Pei-Chun Liao, Jian-Hong Lin, Dawei Heh, WenHsien Kuo
  • Publication number: 20240131808
    Abstract: A tape laying device includes a tape transmission mechanism, a compaction head mechanism, a cutter mechanism, a heating mechanism and a motion mechanism. The tape transmission mechanism is configured to transmit the pre-impregnated tape. The compaction head mechanism, connected with the tape transmission mechanism, is configured to depress and drive the pre-impregnated tape transmitted by the tape transmission mechanism to follow a moving path so as to adhere the pre-impregnated tape onto the mould surface. The cutter mechanism is configured to cut the pre-impregnated tape. The heating mechanism, disposed downstream to the cutter mechanism, is configured to heat the pre-impregnated tape. The motion mechanism is used to have the cutter mechanism having an active path to move toward the moving path while the cutter mechanism cuts the pre-impregnated tape.
    Type: Application
    Filed: December 7, 2022
    Publication date: April 25, 2024
    Inventors: TENG-YEN WANG, SHUN-SHENG KO, MIAO-CHANG WU, TUNG-YING LIN, CHAO-HONG HSU
  • Publication number: 20240136546
    Abstract: A vacuum battery structural assembly and a vacuum multi-cell battery module composed thereof are provided and include a first repeating unit including a first frame plate and a second frame plate with respect to the first frame plate; and an electrolyte channel defined within the first frame plate and the second frame plate to accommodate a liquid electrolyte, wherein both a surface of the first frame plate and a surface of the second frame plate include a vacuum suction area, the vacuum suction area includes a vacuum aperture and a vacuum channel, wherein the vacuum aperture is formed on at least one surface of the first frame plate and the second frame plate, the vacuum channel is positioned inside the first frame plate and the second frame plate, and is configured to generate a longitudinal pressing suction force and seal the first frame plate and the second frame plate.
    Type: Application
    Filed: November 23, 2022
    Publication date: April 25, 2024
    Inventors: Hung-Hsien Ku, Shang-Qing Zhuang, Ning-Yih Hsu, Chien-Hong Lin, Han-Jou Lin, Yi-Hsin Hu, Po-Yen Chiu, Yao-Ming Wang
  • Patent number: 11965898
    Abstract: An automatic nucleic acid detection system and a method thereof are disclosed. The automatic nucleic acid detection method includes: performing, by an automatic control subsystem, on a nucleic acid extraction machine platform, a nucleic acid extraction on one or more specimens in a sample tray to generate one or more corresponding nucleic acids in the sample tray; distributing, by the automatic control subsystem, on a nucleic acid distribution machine platform, the nucleic acid in each hole of the sample tray and a first reagent into a plurality of holes of a detection tray, wherein the number of holes of the detection tray is greater than that of the sample tray; and performing, by the automatic control subsystem, on a nucleic acid detection machine platform, a nucleic acid detection on the detection tray.
    Type: Grant
    Filed: July 23, 2020
    Date of Patent: April 23, 2024
    Assignees: TCI GENE INC, TCI CO., LTD
    Inventors: Yung-Hsiang Lin, Cheng-Hong Hsieh, Ciao-Ting Chen, Tsung-Cheng Chen
  • Publication number: 20240124716
    Abstract: The invention relates to a first curable coating composition comprising a first layer comprising at least one epoxy resin and at least one hybrid nanofiller, and a second layer comprising carbon nanotubes (CNTs). This invention also relates to a second curable coating composition comprising at least one hybrid nanofiller; at least one epoxy resin; and at least one curing agent. This invention also relates to methods of making the curable coating compositions. This invention also relates to methods for coating the surface of a metallic coated substrate.
    Type: Application
    Filed: July 7, 2023
    Publication date: April 18, 2024
    Inventors: Zhibin LIN, Xingyu WANG, Hong PAN
  • Publication number: 20240128179
    Abstract: A package structure includes a first substrate, a second substrate disposed on the first substrate, a third substrate disposed on the second substrate, and multiple chips mounted on the third substrate. A second coefficient of thermal expansion (CTE) of the second substrate is less than a first CTE of the first substrate. The third substrate includes a first sub-substrate, a second sub-substrate in the same level with the first sub-substrate, a third sub-substrate in the same level with the first sub-substrate. A CTE of the first sub-substrate, a CTE of the second sub-substrate, and a CTE of the third sub-substrate are less than the second CTE of the second substrate.
    Type: Application
    Filed: November 8, 2022
    Publication date: April 18, 2024
    Inventors: Jyun-Hong CHEN, Chi-Hai KUO, Pu-Ju LIN, Cheng-Ta KO
  • Publication number: 20240127186
    Abstract: An interaction method and apparatus and an electronic device. The method comprises: displaying a first application interface, wherein the first application interface comprises an interface of a first application; and creating a second application account in the first application interface, wherein the second application account is used for logging in a second application. Therefore, a new interaction mode is provided.
    Type: Application
    Filed: December 21, 2023
    Publication date: April 18, 2024
    Inventors: Xiaoping ZHANG, Yunsheng HAO, Jialu WANG, Yi WEI, Pengzhan XU, Guichao REN, Boyu ZHOU, Zitian GUO, Yuxiang LI, Jieli LIANG, Xiaofei GAO, Daozhi LIN, Hong ZOU, Wentao LIU, Zheng CHEN, Shanshan LING
  • Patent number: 11963347
    Abstract: A memory device includes a transistor, an anti-fuse element, a source/drain contact, a first gate via, and a second gate via. The transistor is over a substrate. The anti-fuse element is over the substrate and is connected to the transistor in series. The source/drain contact is connected to a source/drain region of the transistor. The first gate via is connected to a first gate structure of the transistor. The first gate structure of the transistor extends along a first direction in a top view. The second gate via is connected to a second gate structure of the anti-fuse element. The second gate via is between the first gate via and the source/drain contact along the first direction in the top view.
    Type: Grant
    Filed: April 21, 2023
    Date of Patent: April 16, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Chiung-Ting Ou, Ming-Yih Wang, Jian-Hong Lin
  • Publication number: 20240120854
    Abstract: A triboelectric nanogenerating device is configured for providing an electric power to an electronic device and the triboelectric nanogenerating device includes at least one scaly triboelectric membrane configured for providing the electric power to the electronic device by frictional electrification. The at least one scaly triboelectric membrane includes a keratin and a polyvinyl alcohol, the at least one scaly triboelectric membrane has a first triboelectric surface, and the first triboelectric surface of the at least one scaly triboelectric membrane includes a plurality of scaly layers. Each of the scaly layers is arranged in order and extends along an orienting direction. A distal end of each of the scaly layers has a plurality of saw-tooth structures.
    Type: Application
    Filed: February 6, 2023
    Publication date: April 11, 2024
    Inventors: Zong-Hong Lin, Ming-Zheng Huang, Hsuan-Yu Yeh, An-Rong Chen, Yao-Hsuan Tseng
  • Publication number: 20240117917
    Abstract: A lifting device is provided. The lifting device includes a stationary member, a lifting member, positioning bases, reels, and springs. The lifting member is slidably coupled to the stationary member. The lifting member is fixed to a back portion of the display. The positioning bases are disposed on the stationary member and the lifting member. The reels are pivoted on the positioning bases. The springs are wound around the reels and connected to the other of the stationary member and the lifting member relative to the positioning bases. When the display or the lifting member is subjected to an applied force toward a sliding direction, the lifting member slides toward the sliding direction relative to the stationary member. The springs stretched by the lifting member generate an elastic force, so that the lifting member and the display no longer subjected to a force stay at a height position after sliding.
    Type: Application
    Filed: October 6, 2023
    Publication date: April 11, 2024
    Applicant: AmTRAN TECHNOLOGY Co., Ltd.
    Inventors: Hung-Tse Wang, Jun-Hong Lin
  • Patent number: 11955441
    Abstract: An interconnect structure comprises a first dielectric layer, a first metal layer, a second dielectric layer, a metal via, and a second metal layer. The first dielectric layer is over a substrate. The first metal layer is over the first dielectric layer. The first metal layer comprises a first portion and a second portion spaced apart from the first portion. The second dielectric layer is over the first metal layer. The metal via has an upper portion in the second dielectric layer, a middle portion between the first and second portions of the first metal layer, and a lower portion in the first dielectric layer. The second metal layer is over the metal via. From a top view the second metal layer comprises a metal line having longitudinal sides respectively set back from opposite sides of the first portion of the first metal layer.
    Type: Grant
    Filed: March 28, 2022
    Date of Patent: April 9, 2024
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Jian-Hong Lin, Kuo-Yen Liu, Hsin-Chun Chang, Tzu-Li Lee, Yu-Ching Lee, Yih-Ching Wang
  • Patent number: 11948938
    Abstract: In some embodiments, the present disclosure relates to a semiconductor device comprising a source and drain region arranged within a substrate. A conductive gate is disposed over a doped region of the substrate. A gate dielectric layer is disposed between the source region and the drain region and separates the conductive gate from the doped region. A bottommost surface of the gate dielectric layer is below a topmost surface of the substrate. First and second sidewall spacers are arranged along first and second sides of the conductive gate, respectively. An inner portion of the first sidewall spacer and an inner portion of the second sidewall spacer respectively cover a first and second top surface of the gate dielectric layer. A drain extension region and a source extension region respectively separate the drain region and the source region from the gate dielectric layer.
    Type: Grant
    Filed: July 18, 2022
    Date of Patent: April 2, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-Huan Chen, Chien-Chih Chou, Ta-Wei Lin, Hsiao-Chin Tuan, Alexander Kalnitsky, Kong-Beng Thei, Shi-Chuang Hsiao, Yu-Hong Kuo
  • Patent number: D1026449
    Type: Grant
    Filed: August 24, 2023
    Date of Patent: May 14, 2024
    Inventor: Hong Lin