Abstract: Provided herein are KRAS modulating compounds, such as compounds of Formula (I), (II), (II*), (III) or pharmaceutically acceptable salts, solvates, stereoisomers, atom labelled, or tautomers of any of the foregoing, useful for modulating KRAS GD12 and/or other G12 mutants.

Abstract: Aspects presented herein relate to methods and devices for wireless communication including an apparatus, e.g., a device or a server. The apparatus may detect a set of cells associated with a network node, where each of the set of cells includes a cell ID, where the cell ID for each of the set of cells is associated with a node ID for the network node. The apparatus may also identify a location of each of the set of cells based on the cell ID for each of the set of cells. Additionally, the apparatus may estimate an average location of the set of cells based on the location of each of the set of cells. The apparatus may also calculate a location of the network node based on the average location of the set of cells.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: The invention relates to the synthesis of a carboxyl-functional, unsaturated polyurethane containing a perfluoropolyether block, which can be used as an easy clean additive in preparation of a waterborne, UV curable coating composition. The polyurethane can be prepared by a method comprising the following steps: a) subjecting a hydroxy-terminated perfluoropolyether A to a reaction with a molar excess of polyisocyanate B to obtain an isocyanate-functional urethane C, b) adding a carboxyl-functional polyol D to the reaction mixture, c) adding OH— functional (meth)acrylate monomer E to the reaction mixture, wherein steps (b) and (c) can be performed in any order, and d) neutralizing the reaction product with a neutralizer F. The resulting coating has easy clean and anti-stain properties.

Abstract: Disclosed are techniques for wireless communication. In an aspect, a user equipment (UE) receives, from a location server, a positioning reference signal (PRS) configuration for a downlink-and-uplink-based positioning session between the UE and the location server, waits, based on a determination that a sounding reference signal (SRS) configuration for the downlink-and-uplink-based positioning session has not been received from a serving base station of the UE, for reception of the SRS configuration from the serving base station until expiration of a timer, and determines, based on the expiration of the timer, whether the SRS configuration was received.

Abstract: A semiconductor substrate includes a plurality of transistors. A first structure is disposed over a first side of the semiconductor substrate. The first structure contains a plurality of first metallization components. A carrier substrate is disposed over the first structure. The first structure is located between the carrier substrate and the semiconductor substrate. One or more openings extend through the carrier substrate and expose one or more regions of the first structure to the first side. A second structure is disposed over a second side of the semiconductor substrate opposite the first side. The second structure contains a plurality of second metallization components.

Abstract: A socket of a testing tool is configured to provide testing signals. A device-under-test (DUT) board is configured to provide electrical routing. An integrated circuit (IC) die is disposed between the socket and the DUT board. The testing signals are electrically routed to the IC die through the DUT board. The IC die includes a substrate in which plurality of transistors is formed. A first structure contains a plurality of first metallization components. A second structure contains a plurality of second metallization components. The first structure is disposed over a first side of the substrate. The second structure is disposed over a second side of the substrate opposite the first side. A trench extends through the DUT board and extends partially into the IC die from the second side. A signal detection tool is configured to detect electrical or optical signals generated by the IC die.

Abstract: An integrated circuit (IC) chip assembly includes an integrated circuit (IC) die that includes a first substrate in which plurality of transistors is formed, a first structure that contains a plurality of first metallization components, and a second structure that contains a plurality of second metallization components. The first structure is disposed over a first side of the first substrate. The second structure is disposed over a second side of the first substrate opposite the first side. The chip assembly includes a second substrate bonded to the IC die through the second side. The chip assembly includes a trench that extends through the second substrate and through the second structure of the IC die. Sidewalls of the trench are defined at least in part by one or more protective layers.

Abstract: An apparatus includes first and second microchannel heat exchangers and first and second pipes. The first heat exchanger includes a first inlet, a second inlet, a first tube, a second tube, a first outlet, and a second outlet. Refrigerant at the first inlet is directed through the first tube to the first outlet and the first pipe. Refrigerant at the second inlet is directed through the second tube to the second outlet and the second pipe. The second heat exchanger includes a third inlet, a fourth inlet, a third tube, a fourth tube, a third outlet, and a fourth outlet. The third inlet directs refrigerant from the first pipe through the third tube towards the third outlet. The fourth inlet directs the refrigerant from the second pipe through the fourth tube towards the fourth outlet. The first pipe overlaps the second pipe between the two heat exchangers.

Abstract: A method includes: providing a first semiconductor device including a backside interconnection structure, the first semiconductor device being formed by a semiconductor process; and generating a physical failure analysis model by an inspection process. The inspection process includes: directing an electron beam toward the frontside of the first semiconductor device; and applying an electrical signal to an electrical contact of the first semiconductor device through an electrical path that goes through a shunt board attached to a switchable interface trace bank, the electrical contact being associated with a position of the electron beam. The method further includes: generating a parameter of a revised semiconductor process according to the physical failure analysis model and the semiconductor process; and forming a second semiconductor device by the revised semiconductor process using the parameter.

Abstract: The present disclosure provides bifunctional compounds comprising a target protein binding moiety and a E3 ubiquitin ligase binding moiety, and associated methods of use.

Abstract: A light module driving method for an illumination device, wherein the light module driving method includes an outputting operation of outputting a light driving signal according to a source; a transforming operation of transforming the light driving signal into a plurality of modulated light driving signals according to a compensation and calibration unit; and a driving operation of driving a plurality of lighting zones corresponding to a light-emitting diode (LED) module of the light module according to the plurality of modulated light driving signals.

Abstract: Material properties of graphene can be leveraged to improve performance of interconnects in an integrated circuit. One way to circumvent challenges involved in depositing graphene onto a copper surface is to incorporate graphene into the bulk metal layer to create a hybrid metal/graphene interconnect structure. Such a hybrid structure can be created instead of, or in addition to, forming a graphene film on the metal surface as a metal capping layer. A first method for embedding graphene into a copper damascene layer is to alternate the metal fill process with graphene deposition to create a composite graphene matrix. A second method is to implant carbon atoms into a surface layer of metal. A third method is to disperse graphene flakes in a damascene copper plating solution to create a distributed graphene matrix. Any combination of these methods can be used to enhance conductivity of the interconnect.

Abstract: A graphene-clad metal interconnect extends material properties of graphene to both damascene and patterned interconnect structures at lower metal layers, leading to significant reductions in resistance. Graphene cladding can be used with or without a metal barrier/liner. Presence of a barrier/liner can serve to catalyze growth of an overlying graphene layer. Graphene may also be selectively grown on barrier surfaces. Fully integrated structures and process flows for integrated circuits with graphene-clad metallization are described.

Abstract: An integrated circuit (IC) with through-circuit vias (TCVs) and methods of forming the same are disclosed. The IC includes a semiconductor device, first and second interconnect structures disposed on first and second surfaces of the semiconductor device, respectively, first and second inter-layer dielectric (ILD) layers disposed on front and back surfaces of the substrate, respectively, and a TCV disposed within the first and second interconnect structures, the first and second ILD layers, and the substrate. The TCV is spaced apart from the semiconductor device by a portion of the substrate and portions of the first and second ILD layers. A first end of the TCV, disposed over the front surface of the substrate, is connected to a conductive line of the first interconnect structure and a second end of the TCV, disposed over the back surface of the substrate, is connected to a conductive line of the second interconnect structure.

Abstract: A method for manufacturing a semiconductor device including an upper-channel implant transistor is provided. The method includes forming one or more fins extending in a first direction over a substrate. The one or more fins include a first region along the first direction and second regions on both sides of the first region along the first direction. A dopant is shallowly implanted in an upper portion of the first region of the fins but not in the second regions and not in a lower portion of the first region of the fins. A gate structure extending in a second direction perpendicular to the first direction is formed overlying the first region of the fins, and source/drains are formed overlying the second regions of the fins, thereby forming an upper-channel implant transistor.

Abstract: A semiconductor structure and method of manufacturing a semiconductor structure are provided. The semiconductor structure includes a package structure. The package structure includes a passivation layer formed over an interconnect structure; an electrically-conductive structure formed on the passivation layer and extending through the passivation layer to electrically contact the interconnect structure; a dielectric structure formed over the passivation layer and surrounding the electrically-conductive structure to expose at least a portion of a top surface of the electrically-conductive structure; and a metallic protection structure formed on the top surface of the electrically-conductive structure exposed from the dielectric structure. The top surface of the metallic protection structure is aligned with or lower than a top surface of the dielectric structure.

Abstract: Provided herein are KRAS modulating compounds, such as compounds of Formula (I), (II), (II*), (III) or pharmaceutically acceptable salts, solvates, stereoisomers, atom labelled, or tautomers of any of the foregoing, useful for modulating KRAS GD12 and/or other G12 mutants.

Abstract: In a computer system that includes a set of cross repositories for data storage, a document is broken into portions, and each portion is stored in at least one repository (and preferably many or all of the cross repositories). In this way, when a portion of the document requires an update, the communication of updated data can be limited to the relevant portion(s) of the document. Also, if a user requires only certain portion(s) of the saved document, then the data transfer from a cross repository to the user can be limited to those certain portion(s) of the document.

Abstract: A method for generating offset current values includes: setting a current setting sequence which includes multiple current setting values; driving a light emitting unit and measuring a current value of the light emitting unit; establishing a recurrent neural network (RNN) including an input layer, a hidden layer and an output layer; and inputting the current value into the hidden layer, inputting the current setting values into the input layer sequentially, and obtaining offset values from the output layer sequentially. The offset values correspond to the current setting values respectively.