Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.

Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.

Abstract: The present disclosure provides a hybrid memory system and a method of operating the same. The hybrid memory system includes a non-volatile memory, a volatile memory and a controller. The volatile memory stores data. The controller is configured to move the data from the volatile memory to the non-volatile memory in response to a command to enter a power-saving mode. The controller precludes the volatile memory from having a self-refresh operation performed thereon after the movement of the data.

Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive an inputting data and a temperature signal; a first error-correction code (ECC1) circuit configured to generate a first encoded data from the inputting data; and a second error-correction code (ECC2) circuit configured to generate a second encoded data from the inputting data.

Abstract: The present disclosure provides a dynamic random-access memory (DRAM) with a data correction function and a method of operating the same. The DRAM includes a memory array; a control circuit configured to receive a reading address and a defect information of the reading address; an access circuit configured to generate a reading data from the memory array according to the reading address from the control circuit; and a modifying circuit connected to the access circuit and the control circuit, wherein the modifying circuit is configured to modify a part of the reading data according to the defect information.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.

Abstract: The present disclosure provides a dynamic random access memory (DRAM), and a method of operating the same. The DRAM includes a memory row and a buffer. The memory row is configured to store a data, wherein the memory row does not provide the data to the buffer in response to a request to read the data. The buffer is configured to store the data as a temporarily-stored data, wherein the buffer provides the temporarily-stored data in response to the request.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) including a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data. The second cell is configured to have a stored electrical energy by being programmed with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a refresh rate of the refresh unit to a first refresh rate when the stored electrical energy of the second cell becomes lower than a threshold electrical energy, wherein the threshold electrical energy is higher than a standard electrical energy for determining binary logic.

Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.

Abstract: An operating method of a memory device includes the following operations: during a refresh operation with the first refresh rate, generating a first ECC according to first data, and generating a second ECC according to second data; determining whether an error exists in the first data or not during the refresh operation with a second refresh rate; determining whether the error exists in the second data or not during the refresh operation with a third refresh rate; and if it is determined that the error exists in the first data and/or the second data, correcting the first data and/or the second data. The second refresh rate and the third refresh rate are lower than the first refresh rate, and the third refresh rate is lower than the second refresh rate. The correcting ability of the second ECC is higher than the correcting ability of the first ECC.

Abstract: Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.

Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.

Abstract: Multi-chip wafer level packages and methods of forming the same are provided. A multi-chip wafer level package includes a first tier and a second tier. The first tier includes a first redistribution layer structure and at least one chip over the first redistribution layer structure. The second tier includes a second redistribution layer structure and at least two other chips over the second redistribution layer structure. The first tier is bonded to the second tier with the at least one chip being in physical contact with the second redistribution layer structure. The total number of connectors of the at least two other chips is greater than the total number of connectors of the at least one chip.

Abstract: A dynamic random access memory (DRAM) DRAM includes a memory array, a temperature sensor and a control device. The temperature sensor is configured to sense a temperature of the DRAM. The control device is configured to adjust a sense frequency based on a retention ability of the memory array, and to activate the temperature sensor according to the adjusted sense frequency.