Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.

Abstract: A memory device includes a memory array, an error correction code (ECC) circuit, and a control circuit. The memory array includes plural memory rows and stores a plurality of data. The control circuit is configured to enter the memory device into a power saving mode with a first refresh rate to refresh the memory array, to control the ECC circuit to generate a first ECC according to first data during refreshing the memory array by the first refresh rate, to reduce the first refresh rate to a second refresh rate, to control the ECC circuit to determine whether an error exists in the first data during refreshing the memory array by the second refresh rate. If the error exists in the first data, the control circuit is further configured to control the ECC circuit to correct the first data.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: A dynamic random access memory (DRAM) includes a memory array and a control device. The memory array includes a refresh unit. The refresh unit includes a first cell and a second cell. The first cell is configured to store data, and have a programmed voltage level by being programmed. The second cell is configured to have a test voltage level by being programmed in conjunction with the first cell, wherein the first cell and the second cell are controllable by a same row of the memory array. The control device is configured to increase a voltage difference between the programmed voltage level and a standard voltage level for determining binary logic when the test voltage level becomes lower than a threshold voltage level, wherein the threshold voltage level is higher than the standard voltage level.

Abstract: The present disclosure provides a dynamic random access memory (DRAM) and a method of operating the same. The DRAM includes a memory array, a refresh device and an access device. The refresh device is configured to perform a self-refresh operation on the memory array, wherein the self-refresh operation is interrupted in response to an access command. The access device is configured to access the memory array in response to the access command and the interruption of the self-refresh operation.

Abstract: Integrated fan-out packages and methods of forming the same are disclosed. An integrated fan-out package includes a first semiconductor chip, a plurality of through integrated fan-out vias, an encapsulation layer and a redistribution layer structure. The first semiconductor chip includes a heat dissipation layer, and the heat dissipation layer covers at least 30 percent of a first surface of the first semiconductor chip. The through integrated fan-out vias are aside the first semiconductor chip. The encapsulation layer encapsulates the through integrated fan-out vias. The redistribution layer structure is at a first side of the first semiconductor chip and thermally connected to the heat dissipation layer of the first semiconductor chip.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit, an accessing device and a refresh device. The refresh unit has a plurality of memory rows. The accessing device is configured to access the memory rows. The refresh device is configured to refresh the refresh unit in a first manner in response to a first event, in which a quantity of accessed memory rows of the refresh unit is not greater than a threshold quantity. The refresh device is configured to refresh the refresh unit in a second manner in response to a second event, in which the quantity of accessed memory rows of the refresh unit is greater than the threshold quantity.

Abstract: Present disclosure includes a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of refreshing units, and each of the refreshing units comprises a plurality of word lines for storing data. The system comprises an accessing unit. The accessing unit is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing unit is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.

Abstract: The present disclosure provides a DRAM including a first refresh unit, a second refresh unit, and a control device. The first refresh unit has a first quantity of valid data. The second refresh unit has a second quantity of valid data less than the first quantity of valid data. The control device is configured to determine that the first refresh unit has a greater quantity of valid data than the second refresh unit, move valid data of the second refresh unit into the first refresh unit, and cease refreshing the second refresh unit whose valid data was moved into the first refresh unit.

Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array and a control device. The memory array has a plurality of word lines configured to control memory cells. The control device is configured to operate at least one word line of the word lines, derive an information on the operating of the at least word line, and cease maintaining data stored in the memory cells controlled by the at least one word line when the information satisfies a condition.

Abstract: An integrated fan-out package includes a first redistribution structure, a die, an encapsulant, a plurality of conductive structures, and a second redistribution structure. The first redistribution structure has a first surface and a second surface opposite to the first surface. The die is disposed over the first surface of the first redistribution structure and is electrically connected to the first redistribution structure. The encapsulant encapsulates the die. The conductive structures are disposed on the first surface of the first redistribution structure and penetrates the encapsulant. The conductive structures surround the die. The second redistribution structure is disposed on the encapsulant and is electrically connected to the first redistribution structure through the conductive structures. The second redistribution structure includes at least one conductive pattern layer that is in physical contact with the encapsulant.

Abstract: Present disclosure relates to a system for preserving data in a volatile memory and a method thereof. The volatile memory comprises a plurality of word lines for storing data. The system comprises an accessing detector. The accessing detector is configured to detect a row-hammer indication indicating a first word line is frequently accessed, wherein the accessing detector is configured to copy data stored in the first word line to a second word line when the row-hammer indication is detected on the first word line, wherein the data stored in the first and the second word lines are available to be selectively accessed.

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.

Abstract: A method includes forming a redistribution structure over a carrier, the redistribution structure having conductive features on a surface of the redistribution structure distal the carrier; forming a conductive pillar over the surface of the redistribution structure; attaching a die to the surface of the redistribution structure adjacent to the conductive pillar, where die connectors of the die are electrically coupled to the conductive features of the redistribution structure; and attaching a pre-made substrate to the conductive pillar through a conductive joint, where the conductive joint is on the conductive pillar and comprises a different material from the conductive pillar, where the conductive joint and the conductive pillar electrically couple the redistribution structure to the pre-made substrate.

Abstract: Package structures and methods for forming the same are provided. A package structure includes a semiconductor die. The semiconductor die includes a passivation layer over a semiconductor substrate. The semiconductor die also includes a conductive pad in the passivation layer. The passivation layer partially exposes a top surface of the conductive pad. The package structure also includes an encapsulation layer surrounding the semiconductor die. The package structure further includes a dielectric layer covering the semiconductor die and the encapsulation layer. In addition, the package structure includes a redistribution layer covering the dielectric layer. The redistribution layer extends in the dielectric layer to be physically connected to the top surface of the conductive pad.

Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.

Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a plurality of banks, a power source and a control device. Each of the banks includes a plurality of subarrays. The control device derives information on a quantity of operated subarrays among the subarrays, and determines how much electrical energy to provide based on the information. The power source provides the resultant amount of electrical energy based on the determination from the control device.

Abstract: The present disclosure provides a dynamic random access memory (DRAM). The DRAM includes a refresh unit and an accessing device. The refresh unit includes a target row on which a read/write (R/W) operation is requested to be performed. The accessing device is configured to perform the R/W operation on the target row while the refresh unit is being refreshed.

Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.