Patents by Inventor Hsien-Wen Liu

Hsien-Wen Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Structure and formation method for chip package
    Patent number: 10074637
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: March 14, 2017
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Wafer level package (WLP) and method for forming the same
    Patent number: 10074617
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: December 12, 2016
    Date of Patent: September 11, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • DRAM and method for managing power thereof
    Patent number: 10049714
    Abstract: The present disclosure provides a DRAM. The DRAM includes a memory array of memory cells, a control device and a charge pump circuit. The control device derives an information associated with a command, and determine, based on the information, whether to provide an amount of electrical energy greater than, less than, or equal to an amount of electrical energy currently required. The charge pump circuit provides the memory array with the resultant amount of electrical energy based on the determination.
    Type: Grant
    Filed: July 19, 2017
    Date of Patent: August 14, 2018
    Assignee: NANYA TECHNOLOGY CORPORATION
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • Dram and method for accessing a dram
    Patent number: 10019350
    Abstract: The present disclosure provides a method. The method includes copying a data stored in memory cells associated with a normal word line subject to a row hammer effect into memory cells associated with a hot word line before a condition is satisfied, wherein the condition includes an access frequency of the normal word line reaching a threshold frequency; accessing, based on a logical address, the normal word line before the condition is satisfied; accessing, based on the logical address, the hot word line associated with the copied data only if the condition is satisfied; and accessing the data no longer from the normal word line only if the condition is satisfied.
    Type: Grant
    Filed: August 2, 2017
    Date of Patent: July 10, 2018
    Assignee: Nanya Technology Corporation
    Inventors: Chung-Hsun Lee, Hsien-Wen Liu
  • PACKAGE STRUCTURE AND METHOD FOR FORMING THE SAME
    Publication number: 20180166396
    Abstract: Package structures and methods for forming the same are provided. A fan-out package structure includes a semiconductor substrate. The package structure also includes a connector over a top surface of the semiconductor substrate. The package structure further includes a buffer layer surrounding the connector and overlying a sidewall of the semiconductor substrate. In addition, the package structure includes an encapsulation layer surrounding the buffer layer. The buffer layer is between the encapsulation layer and the sidewall of the semiconductor substrate. The package structure also includes a redistribution layer (RDL) over the buffer layer and the encapsulation layer. The redistribution layer is electrically connected to the connector.
    Type: Application
    Filed: July 3, 2017
    Publication date: June 14, 2018
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsiao-Wen LEE, Hsien-Wen LIU, Shin-Puu JENG
  • STACKED SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME
    Publication number: 20180151512
    Abstract: A semiconductor device includes: a first dielectric layer having a first surface; a molding compound disposed on the first surface of the first dielectric layer; a second dielectric layer having a first surface disposed on the molding compound; a via disposed in the molding compound; and a first conductive bump disposed on the via and surrounded by the second dielectric layer; wherein the first dielectric layer and the second dielectric layer are composed of the same material. The filling material has a thickness between the second dielectric layer and the semiconductor die, and the diameter of the hole is inversely proportional to the thickness of the filling material.
    Type: Application
    Filed: April 12, 2017
    Publication date: May 31, 2018
    Inventors: SHIN-PUU JENG, TZU-JUI FANG, HSI-KUEI CHENG, CHIH-KANG HAN, YI-JEN LAI, HSIEN-WEN LIU, YI-JOU LIN
  • Molding chamber apparatus and curing method
    Patent number: 9950450
    Abstract: An embodiment is a molding chamber. The molding chamber comprises a mold-conforming chase, a substrate-base chase, a first radiation permissive component, and a microwave generator coupled to a first waveguide. The mold-conforming chase is over the substrate-base chase, and the mold-conforming chase is moveable in relation to the substrate-base chase. The first radiation permissive component is in one of the mold-conforming chase or the substrate-base chase. The microwave generator and the first waveguide are together operable to direct microwave radiation through the first radiation permissive component.
    Type: Grant
    Filed: October 29, 2014
    Date of Patent: April 24, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Chen-Hua Yu, Shin-Puu Jeng, Jui-Pin Hung, Hsien-Wen Liu
  • USING METAL-CONTAINING LAYER TO REDUCE CARRIER SHOCK IN PACKAGE FORMATION
    Publication number: 20180033782
    Abstract: A method includes forming a dielectric layer over a radiation de-bondable coating. The radiation de-bondable coating is over a carrier, and the radiation de-bondable coating includes metal particles therein. Metal posts are formed over the dielectric layer. A device die is attached to the dielectric layer. The device die and the metal posts are encapsulated in an encapsulating material. A plurality of redistribution lines is formed on a first side of the encapsulating material, and is electrically coupled to the device die and the metal posts. The carrier is de-bonded by projecting a radiation source on the radiation de-bondable coating to decompose the radiation de-bondable coating. Electrical connections are formed on a second side of the encapsulating material. The electrical connections are electrically coupled to the metal posts.
    Type: Application
    Filed: July 29, 2016
    Publication date: February 1, 2018
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu, Yi-Jou Lin
  • Integrated fan-out package on package structure and methods of forming same
    Patent number: 9881908
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Grant
    Filed: January 15, 2016
    Date of Patent: January 30, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Integrated Fan-Out Package on Package Structure and Methods of Forming Same
    Publication number: 20170207204
    Abstract: An embodiment package includes a first package; a thermal interface material (TIM) contacting a top surface of the first package, and a second package bonded to the first package. The second package includes a first semiconductor die, and the TIM contacts a bottom surface of the first semiconductor die. The package further includes a heat spreader disposed on an opposing surface of the second package as the first package.
    Type: Application
    Filed: January 15, 2016
    Publication date: July 20, 2017
    Inventors: Wen-Yi Lin, Hsien-Wen Liu, Po-Yao Lin, Cheng-Lin Huang, Shyue-Ter Leu, Shin-Puu Jeng
  • Structure and Formation Method for Chip Package
    Publication number: 20170186736
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Application
    Filed: March 14, 2017
    Publication date: June 29, 2017
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Integrated Circuit Structure and Method for Reducing Polymer Layer Delamination
    Publication number: 20170170161
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Application
    Filed: February 27, 2017
    Publication date: June 15, 2017
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Methods for molding integrated circuits
    Patent number: 9662812
    Abstract: A method includes molding a polymer onto a package component. The step of molding includes a first molding stage performed at a first temperature, and a second molding stage performed at a second temperature different from the first temperature.
    Type: Grant
    Filed: May 31, 2012
    Date of Patent: May 30, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Hao Chen, Hsien-Wen Liu, Yi-Lin Tsai, Jui-Pin Hung, Jing-Cheng Lin
  • Wafer Level Package (WLP) and Method for Forming the Same
    Publication number: 20170092597
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Application
    Filed: December 12, 2016
    Publication date: March 30, 2017
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Structure and formation method for chip package
    Patent number: 9595510
    Abstract: Structures and formation methods of a chip package are provided. The chip package includes a semiconductor die and a package layer partially or completely encapsulating the semiconductor die. The chip package also includes a conductive feature penetrating through the package layer. The chip package further includes an interfacial layer the interfacial layer continuously surrounds the conductive feature. The interfacial layer is between the conductive feature and the package layer, and the interfacial layer is made of a metal oxide material.
    Type: Grant
    Filed: October 13, 2015
    Date of Patent: March 14, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jui-Pin Hung, Cheng-Lin Huang, Hsien-Wen Liu, Shin-Puu Jeng
  • Integrated circuit structure and method for reducing polymer layer delamination
    Patent number: 9583424
    Abstract: An embodiment integrated circuit structure includes a substrate, a metal pad over the substrate, a post-passivation interconnect (PPI) structure over the substrate and electronically connected to the metal pad, a first polymer layer over the PPI structure, an under bump metallurgy (UBM) extending into an opening in the first polymer layer and electronically connected to the PPI structure, and a barrier layer on a top surface of the first polymer layer adjacent to the UBM.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: February 28, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jing-Cheng Lin, Jui-Pin Hung, Hsien-Wen Liu, Min-Chen Lin
  • Patch antenna and wireless communication device using the same
    Patent number: 9531056
    Abstract: A patch antenna includes an irradiation plate, a grounding point and a feeding point. The irradiation plate has a long edge. The grounding point is located at the long edge. The feeding point is located at the long edge. The grounding point and the feeding point are symmetrical with respect to a center of the long edge.
    Type: Grant
    Filed: December 1, 2014
    Date of Patent: December 27, 2016
    Assignee: SERCOMM CORPORATION
    Inventors: Hsien-Wen Liu, Feng-Yu Lin, Ching-Hung Chen
  • Wafer level package (WLP) and method for forming the same
    Patent number: 9520372
    Abstract: A semiconductor device structure and method for forming the same are provided. The semiconductor device structure includes a substrate and a conductive pad formed on the substrate. The semiconductor device structure includes a protection layer formed over the conductive pad and a post-passivation interconnect (PPI) structure formed at least in the protection layer. The PPI structure is electrically connected to the conductive pad. The semiconductor device structure also includes a first moisture-resistant layer formed over the protection layer, and the protection layer and the first moisture-resistant layer are made of different materials. The semiconductor device structure further includes an under bump metallurgy (UBM) layer formed over the first moisture-resistant layer and connected to the PPI structure.
    Type: Grant
    Filed: August 27, 2015
    Date of Patent: December 13, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Shin-Puu Jeng, Hsien-Wen Liu
  • Multi-antenna structure
    Patent number: 9300034
    Abstract: A multi-antenna structure includes a base plate, a first antenna, a second antenna, a first metal line, and a second metal line. The base plate includes a grounded metal surface. The grounded metal surface includes two short sides and two long sides. The first antenna and the second antenna are arranged on the base plate. The first metal line and the second metal line are electrically connected to the two short sides of the grounded metal surface. A current path of the two short sides is prolonged because of the first metal line and the second metal line. A longitudinal current is equal to a transverse current at a low frequency. A current of the first antenna and a current of the second antenna does not interfere each other. Isolation between the first antenna and the second antenna is improved.
    Type: Grant
    Filed: July 5, 2013
    Date of Patent: March 29, 2016
    Assignee: AUDEN TECHNO. CORP.
    Inventors: Chun-Hua Chen, Hsien-Wen Liu
  • Method for forming crack stop structure
    Patent number: 9287221
    Abstract: A semiconductor structure includes a matrix, an integrated circuit and a scribe line. The matrix includes a scribe line region and a circuit region. The integrated circuit is disposed within the circuit region. The scribe line is disposed within the scribe line region and includes a crack stop trench which is disposed in the matrix and adjacent to the circuit region. The crack stop trench is parallel with one side of the circuit region and filled with a composite material in a form of a grid to form a crack stop structure.
    Type: Grant
    Filed: January 7, 2015
    Date of Patent: March 15, 2016
    Assignee: NANYA TECHNOLOGY CORP.
    Inventors: Tse-Yao Huang, Yi-Nan Chen, Hsien-Wen Liu