Abstract: In a method of diagnosing an RF generator of a laser produced plasma extreme ultra violet (LPP EUV) radiation source apparatus, a testing system is connected to the RF generator of the LPP EUV radiation source apparatus. An output power is measured by the testing system with changing an input power of the RF generator. Using a computer system, the measured output power is analyzed. Based on the analyzed measured output power, whether the RF generator is operating properly is determined.

Abstract: A semiconductor device includes: a first conductive structure that comprises a first portion having sidewalls and a bottom surface, wherein the first conductive structure is embedded in a first dielectric layer; and an isolation layer comprising a first portion and a second portion, wherein the first portion of the isolation layer lines the sidewalls of the first portion of the first conductive structure, and the second portion of the isolation layer lines at least a portion of the bottom surface of the first portion of the first conductive structure.

Abstract: Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

Abstract: Methods, circuits, devices, and systems for high voltage electrostatic discharge (ESD) protection are provided. An example ESD protection device includes: a base well of a first dopant type on a substrate, a first well of the first dopant type in the base well, a second well of a second dopant type in the base well, a first highly doped region of the first dopant type and a second highly doped region of the second dopant type in the first well, a third highly doped region of the second dopant type in the second well, and a fourth highly doped region of the first dopant type in the third highly doped region. The first highly doped region and the second highly doped region are coupled to a first voltage terminal, and the third highly doped region and the fourth highly doped region are coupled to a second voltage terminal.

Abstract: An electrostatic discharge protection device includes: a semiconductor substrate; an N-type doped well on the substrate, the N-type doped well including a first N+ region and a first P+ region; a P-type doped well on the substrate, the P-type doped well including a second N+ region, a third N+ region, and a second P+ region between the second N+ region and the third N+ region; and a first contact positioned above a surface of the N-type doped well between the first N+ region and the first P+ region.

Abstract: Methods, circuits, devices, and systems for high voltage electrostatic discharge (ESD) protection are provided. An example ESD protection device includes: a base well of a first dopant type on a substrate, a first well of the first dopant type in the base well, a second well of a second dopant type in the base well, a first highly doped region of the first dopant type and a second highly doped region of the second dopant type in the first well, a third highly doped region of the second dopant type in the second well, and a fourth highly doped region of the first dopant type in the third highly doped region. The first highly doped region and the second highly doped region are coupled to a first voltage terminal, and the third highly doped region and the fourth highly doped region are coupled to a second voltage terminal.

Abstract: An electrical static discharge (ESD) protection device and a method for ESD are provided. The ESD protection device includes first and second wells and fourth through sixth doped regions. The first and second wells are located in a substrate. The first well has first through third doped regions, so as to form a first transistor. The second well is located aside the first well. The fourth through sixth doped regions are located in the second well. The fourth doped region is contacted with the third doped region. A conductive type of the fourth doped region is the same with a conductive type of the third doped region. The fifth doped region, the second well and the substrate forms a second transistor, of which a conductive type is complementary to a conductive type of the first transistor. The fifth doped region is located between the fourth and sixth doped regions.

Abstract: An electronic device includes a casing, a first power housing and a second power housing. The casing is equipped with a main board. The first power housing is disposed in the casing. The first power housing has a plurality of engaging portions. The second power housing has a plurality of engaging grooves. Each of the engaging grooves is corresponding to one of the engaging portions. Each of the engaging grooves is L-shaped and has an opening. When the second power housing is disposed on the first power housing and the engaging portion enters the engaging groove through the opening, the second power housing is capable of moving with respect to the first power housing in a horizontal direction, such that the engaging portion is engaged with the engaging groove.

Abstract: An electronic device includes a casing, a first power housing and a second power housing. The casing is equipped with a main board. The first power housing is disposed in the casing. The first power housing has a plurality of engaging portions. The second power housing has a plurality of engaging grooves. Each of the engaging grooves is corresponding to one of the engaging portions. Each of the engaging grooves is L-shaped and has an opening. When the second power housing is disposed on the first power housing and the engaging portion enters the engaging groove through the opening, the second power housing is capable of moving with respect to the first power housing in a horizontal direction, such that the engaging portion is engaged with the engaging groove.

Abstract: An assembly mechanism and a server system therewith are disclosed. The server system includes a casing, a first module and a second module. The first module is installed inside the casing. The second module is selectively installed inside the casing. The assembly mechanism includes a frame mechanism, a tray, a first fixing member and a handle member. The frame mechanism is disposed around the first module. The tray is combined with the second module and supports the second module above the first module cooperatively with the frame mechanism. The first fixing member is fixed on the frame mechanism. The handle member is pivoted to the tray. The handle member activates the tray to approach the first module as being rotated in a first direction. The handle member activates the tray to separate from the first module as being rotated in a second direction.

Abstract: A high frequency plasma apparatus includes a reaction chamber, a first electrode, a second electrode, and a plurality of feed points located at one of the two electrodes at least. The feed points are used to simultaneously generate a first standing wave and a second standing wave, with different temporal and spatial patterns. By adjusting amplitudes of the two standing waves and the temporal and spatial phase differences between the two standing waves appropriately, plasma uniformity of the high frequency plasma apparatus can be effectively improved.

Abstract: A manufacturing method of a semiconductor structure provides a substrate. A well having a first conductive type and a well having a second conductive type are formed in the substrate, respectively. A body region is formed in the well having the second conductive type. A first doped region and a second doped region are formed in the well having the first conductive type and the body region respectively. The first and second doped regions have same polarities, and a dopant concentration of the second doped region is higher than that of the first doped region. A third doped region is formed in the well having the second conductive type and between the first and second doped regions. The third and first doped regions have reverse polarities. A first field plate is formed on a surface region between the second and third doped regions.

Abstract: A semiconductor device includes high-voltage (HV) and low-voltage (LV) MOS's formed in a substrate. The HV MOS includes a first semiconductor region having a first-type conductivity and a first doping level, a second semiconductor region having the first-type conductivity and a second doping level lower than the first doping level, a third semiconductor region having a second-type conductivity, and a fourth semiconductor region having the first-type conductivity. The first, second, third, and fourth semiconductor regions are arranged along a first direction, and are drain, drift, channel, and source regions, respectively, of the HV MOS. The LV MOS includes the fourth semiconductor region, a fifth semiconductor region having the second-type conductivity, and a sixth semiconductor region having the first-type conductivity.

Abstract: Provided is a semiconductor device including a gate structure, a first doped region of a first conductivity type, a plurality of second doped regions of a second conductivity type, a third doped region of the first conductivity type, and a plurality of fourth doped regions of the second conductivity type. The gate structure is located on a substrate. The first doped region is located in the substrate on a first side of the gate structure. The second doped regions are located in the first doped region. The second doped regions are separated from each other. The third doped region is located in the substrate on a second side of the gate structure. The fourth doped regions are located in the third doped region. The fourth doped regions are separated from each other. The second doped regions and the fourth doped regions are disposed alternately.

Abstract: A semiconductor device formed in a substrate, including a first region, a second region formed over the first region, a third region, a fourth region formed over the third region, and a fifth region formed over the first region and contacting the second region. The first, second, and fourth regions have a first-type conductivity, and constitute drain region, drain electrode, and source region of a metal-on-semiconductor (MOS) structure. The second region has a higher doping level than the first region. The third region has a second-type conductivity and constitutes channel and body regions of the MOS structure. The fifth region has the second-type conductivity and constitutes an emitter region of a bipolar junction (BJ) structure. The second and third regions constitute base and collector regions of the BJ structure.

Abstract: A semiconductor device includes first metal-on-semiconductor (MOS), second MOS, and bipolar junction (BJ) structures formed in a substrate. The first MOS structure includes first drain, first channel, and first source regions arranged along a first direction. The first MOS structure further includes a drain electrode formed over and conductively coupled to the first drain region, and a body region formed below and conductively coupled to the channel region. The second MOS structure includes second drain, second channel, and second source regions arranged along a second direction different from the first direction. The BJ structure includes emitter, base, and collector regions. The first source region and the second drain region share a first common semiconductor region in the substrate. The drain electrode and the base region share a second common semiconductor region in the substrate. The body region and the collector region share a third common semiconductor region in the substrate.

Abstract: A large-area plasma generating apparatus is disclosed, which includes a reaction chamber; a first electrode disposed in the reaction chamber; a second electrode parallel with the first electrode and disposed in the reaction chamber; and a discharge region formed between the first and second electrodes and a plasma can be formed therein; wherein a travelling wave or a traveling-wave-like electromagnetic field is generated via at least one of the first and second electrodes and travels from one end of the discharge region to its opposite end, so as to uniform the plasma in the discharge region.

Abstract: A semiconductor element and a manufacturing method and an operating method of the same are provided. The semiconductor element includes a substrate, a first well, a first heavily doping region, at least a second heavily doping region, a gate layer, a third heavily doping region, and a fourth heavily doping region. The first well and the third heavily doping region are disposed on the substrate. The first and fourth heavily doping regions are disposed in the first well. The second heavily doping region is disposed in the first heavily doping region. The gate layer is disposed on the first well. The first, third, and fourth heavily doping regions having a first type doping are separated from one another. The first well and the second heavily doping region have a second type doping complementary to the first type doping.

Abstract: A semiconductor device including metal-on-semiconductor (MOS) and bipolar junction (BJ) structures formed in a substrate. The MOS structure includes a first region, a second region formed over the first region, a third region, and a fourth region formed over the third region. The first, second, and fourth regions have a first-type conductivity, being drain region, drain electrode, and source region of the MOS structure. Doping level of the second region is higher than that of the first region. The third region has a second-type conductivity, including channel and body regions of the MOS structure. The channel region is formed between the first and fourth regions. The BJ structure includes a fifth region formed over the first region, contacting the second region, having the second-type conductivity, and being an emitter region of the BJ structure. The second and third regions are base and collector regions of the BJ structure.

Abstract: A high voltage semiconductor device is provided, comprising a high voltage metal-oxide-semiconductor transistor (HVMOS), and a normally-on low voltage metal-oxide-semiconductor transistor (LVMOS) electrically connected to the HVMOS. The HVMOS has a first collector and a first emitter, and the LVMOS has a second collector and a second emitter, wherein the second collector of the LVMOS is electrically connected to the first emitter of the HVMOS. The LVMOS electrically connected to the HVMOS provides an electro-static discharge bipolar transistor (ESD BJT), such as a NPN-type ESD BJT.